Faw
Guest
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 Posted:
Wed Sep 28, 2005 8:15 am Post subject:
APB bridge |
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Hi,
In AMBA bus architecture (like most other bus architecture), they have
AHB for high speed communication and APB for slower peripheral
communication. For syhchronization purpose, APB bridge is used.
I was wondering, when a processor on the AHB reads data from a UART
sitting on the APB, what actually happens in terms of timing?
For example, AHB is 200 MHz and APB is 20 MHz. During this read cycle,
let say it takes two clock cycles in AHB to deliver address and also
two clock cycles in APB to capture that address and respond with read
data on APB bus. Remember that APB clock duration is equal to 10 AHB
clock.
So, in this case...what actually happens?
1. Does the processor wait idly until APB bridge response during the
whole write cycle?
2. Do they implement SPLIT transfer, where the processor would go do
some other things until the bridge signals it's readiness to provide
read data?
Or any other scenario?
Unfortunately the specification documents (rev.2, 1999) do not explain
this. At least I didn't find it. |
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jon@beniston.com
Guest
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| Posted:
Thu Sep 29, 2005 12:15 am Post subject:
Re: APB bridge |
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| Quote: | So, in this case...what actually happens?
1. Does the processor wait idly until APB bridge response during the
whole write cycle?
2. Do they implement SPLIT transfer, where the processor would go do
some other things until the bridge signals it's readiness to provide
read data?
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It depends on the AHB/APB bridge and AHB master. Not all bridges (AHB
slaves) support split transfers. Not all masters will have something
else to do (and there may only be one master). I've seen systems that
do 1, and systems that do 2.
Cheers,
Jon |
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