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Oliver S.
Guest
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 Posted:
Thu Oct 06, 2005 4:15 pm Post subject:
Timing of the PAUSE-instruction on Prescot P4s and Xeons |
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Unbelievably! My news-Provider (news.arcor.de) locked my account
and canceled my first posting. Maybe it's because of I posted my
first posting with an attachment, maybe ist's because I started
to flame an idiot in another german thread; but it's nothing for
which I would lock someone's account. So be aware of this fuddy
-duddy-ness of Arcor when you consider to use this Arcor-service.
Ok, so here is my article for a second time:
Intel has introduced an additional instruction with the Prescott core
of the Pentium-4. This instruction is intended to reduce the consump-
tion of CPU-power while spinning for a mutex-lock (ML). Spinning on a
ML for an appropriate number of rounds can prevent a kernel transition
of the thread trying to acquire the ML in almost any case when the ML
is held only a very short period (like when inserting an item into a
producer/consumer-queue). When this instruction is used properly with-
in a spin-wait-loop, the effect is that the pipeline is sopped for a
short while to reduce the power-consumption of the CPU.
I didn't find any information on how many cycles of idleness a pause
instruction introduces. And I suspect that this may vary on the type
of Processor, i.e. P4-Northwood vs Xeon-Northwood, the current confi-
guration, i.e. the number of processors enabled through the BIOS and
if hyperthreading is enabled, and if the processor dynamically obser-
ves, that the cache-line holding a ML's lock-flag got evicted from
the cache because another CPU requested exclusive ownership; the
latter case may make sense to reduce the load on the FSB and thereby
improve the system's overall performance.
I've written a little Win32-program that tests the performance of a
simple spin-loop in a single thread and in two threads runnning on two
different processors if the program runs on a SMP-system (I hope I've
used the SetThreadAffinityMask-function properly to hit two different
physical processors and not the two siblings of a single HT-core *g*).
The process sets itself to REALTIME_PRIORITY_CLASS and all spawned
threads to THREAD_PRIORITY_TIME_CRITICAL to cause all threads running
on priority 31 so that it won't be interrupted by anything more than
interrupts or deferred-procedure-calls of the kernel (hopefully you
won't run any software that does the same and thereby contend for
execution time with my program *g*).
As I currently don't own any webspace, I've simply misused the ser-
vice www.putfile.com for uploading a .tar.gz-file in disguise, i.e.
by giving it the extension .gif. So after downloading, change the
extension to .tar.gz to be able to defalte this archive. It contains
the source of the program and the compiled .exe-cutable (compiled
with "cl /Ox PauseInstruction.cpp" with Visual-Studio-.NET 2003).
It would be nice to see results from the following machines an confi-
gurations:
- single-processor Prescott P4s with HT enabled and disabled,
- dual Prescott-Xeons with HT enabled and disabled,
- dual Prescott-Xeons with the second processor disabled,
- dual Prescott-Xeons with HT and the second processor disabled
and
- maybe even MP-Xeons that base on a prescott-derivate (if such
a core exists) in the same configurations like the Prescott-Xeon.
P.S.: I've posted this article on a number of newsgroups I thought
it would be appropriate. Please drop other newsgroups than the ger-
man newsgroup ger.ct (a german newsgroup with some competent geeks)
from any FUp only if you wrote a follow-up in german. And please
drop the other NGs only if you've got a good reason for that. |
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Oliver S.
Guest
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| Posted:
Thu Oct 06, 2005 4:15 pm Post subject:
Re: Timing of the PAUSE-instruction on Prescot P4s and Xeons |
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Aaaaaah, I forgot to mention the link to the disguised .gif-file:
http://x7.putfile.com/10/27807460022.gif
If your browser doesn't support to save a .gif-file which isn't
really a .gif-file, simply download the file with any download
-manager or wget. |
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Oliver S.
Guest
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| Posted:
Thu Oct 06, 2005 4:15 pm Post subject:
Re: Timing of the PAUSE-instruction on Prescot P4s and Xeons |
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Oh, I would be very pleased if anyone would be so nice to
port this tiny app to any x86-(64)-Unix or -Linux-derivate. |
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Ulrich Eckhardt
Guest
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| Posted:
Sat Oct 08, 2005 8:15 am Post subject:
Re: Timing of the PAUSE-instruction on Prescot P4s and Xeons |
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Oliver S. wrote:
| Quote: | Unbelievably! My news-Provider (news.arcor.de) locked my account
and canceled my first posting. Maybe it's because of I posted my
first posting with an attachment, maybe ist's because I started
to flame an idiot in another german thread; but it's nothing for
which I would lock someone's account.
|
No, sorry, it's because you're a jerk too stupid to first read about how to
use the Usenet. These three your postings here wouldn't be missed by
anyone, too, if they were cancelled.
For the sake of adding constructive criticism, read up on google,
nettiquette, top-posting (formatting styles in general), (binary)
attachments in the Usenet, cross-posting dos and don'ts. Then lurk for a
month or two until you know how things run. Then, maybe, post again, but
not earlier.
Uli |
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Oliver S.
Guest
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| Posted:
Sat Oct 08, 2005 4:15 pm Post subject:
Re: Timing of the PAUSE-instruction on Prescot P4s and Xeons |
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| Quote: | No, sorry, it's because you're a jerk too stupid to first read
about how to use the Usenet. These three your postings here wouldn't
be missed by anyone, too, if they were cancelled.
For the sake of adding constructive criticism, read up on google,
nettiquette, top-posting (formatting styles in general), (binary)
attachments in the Usenet, cross-posting dos and don'ts. Then lurk
for a month or two until you know how things run. Then, maybe, post
again, but not earlier.
|
Typical german flame-posting! |
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