Joe Pfeiffer
Guest
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 Posted:
Thu Oct 20, 2005 10:46 pm Post subject:
Re: Memory to Processor |
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"friend.05@gmail.com" <hirenshah.05@gmail.com> writes:
| Quote: | I am one doubt regarding porcessor.
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All of this is completely processor-specific, so any answer has to be
a bit general... it's likely there are machines that do differently
than I say here for just about every answer I'm giving.
| Quote: | when an access to memory is performed for read operation, how
microprocessors know how much data the memory sends them?
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Most of the time, the memory sends the processor the right amount of
data to fill one cache line. Because this is part of the
specification, the processor knows this is how much to expect.
Basically, the wires are there to transfer that much memory, and it
doesn't cost any more to use them all than to leave them idle. So
they might as well all be used.
| Quote: |
i think there some signal called port size indicator which is send my
memory to processors.
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Most of the time, this is relevant to IO ports, where the device might
be expecting to send 8, 16, or 32 bits depending on the device and a
host of other factors. But again, it's the process who tells the
device how much data to send, and the device responds with the
requested amount.
| Quote: | can anyone explain me same in detail. i am don't have any idea about
such signals.
and during write operations also does any signal send my memory to
processor
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Typically, no. Though in a system with a write-back cache, a process
write requires the cache to read a line from memory so the data being
written by the processor can be put in a valid cache line.
--
Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605
Department of Computer Science FAX -- (505) 646-1002
New Mexico State University http://www.cs.nmsu.edu/~pfeiffer
skype: jjpfeifferjr |
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