| Author |
Message |
Faw
Guest
|
 Posted:
Fri Oct 21, 2005 8:15 am Post subject:
Fall-through stack |
|
|
Hi,
I'm trying to understand the circuit operation of a FIFO buffer memory.
One such example is, 74F433 from National Semiconductor or Fairchild.
The datasheet describes nicely the input and output buffers, but gives
almost no information about the fall-through stack.
Please give me some light on how the fall-through operation works (in
general, or related to 74F433). Much more helpful if you can include
some schematics. If there is an existing document describing it, please
point me to the document. Appreciate any input that you might have.
Thanks. |
|
| Back to top |
|
 |
Del Cecchi
Guest
|
| Posted:
Fri Oct 21, 2005 4:15 pm Post subject:
Re: Fall-through stack |
|
|
Faw wrote:
| Quote: | Hi,
I'm trying to understand the circuit operation of a FIFO buffer memory.
One such example is, 74F433 from National Semiconductor or Fairchild.
The datasheet describes nicely the input and output buffers, but gives
almost no information about the fall-through stack.
Please give me some light on how the fall-through operation works (in
general, or related to 74F433). Much more helpful if you can include
some schematics. If there is an existing document describing it, please
point me to the document. Appreciate any input that you might have.
Thanks.
What you gonna use the answer for? I can think of a couple ways to do |
it. Isn't there a diagram in some manual, or an app note?
If it isn't documented, there is no way to tell. Is there a simulation
model? Verilog?
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.” |
|
| Back to top |
|
|
Karl Olsen
Guest
|
| Posted:
Sat Oct 22, 2005 12:15 am Post subject:
Re: Fall-through stack |
|
|
"Faw" <fawnizu@gmail.com> wrote in message
news:1129874440.229135.292680@g43g2000cwa.googlegroups.com...
| Quote: | I'm trying to understand the circuit operation of a FIFO buffer memory.
One such example is, 74F433 from National Semiconductor or Fairchild.
The datasheet describes nicely the input and output buffers, but gives
almost no information about the fall-through stack.
Please give me some light on how the fall-through operation works (in
general, or related to 74F433). Much more helpful if you can include
some schematics. If there is an existing document describing it, please
point me to the document. Appreciate any input that you might have.
|
My 74HC/HCT databook has some schematic of the 74HC(T)40105 4x16 FIFO.
Karl Olsen |
|
| Back to top |
|
|
Faw
Guest
|
| Posted:
Sun Oct 23, 2005 9:58 pm Post subject:
Re: Fall-through stack |
|
|
Del Cecchi,
I need the understanding to construct a slightly functionally different
FIFO buffer for my research. So, I needed to know how the fall-through
functionality work. I'll check out 74HC(T)40105 4x16 FIFO datasheet
recommended by Karl Olsen below (Thanks Karl!). But in the meantime, if
you can briefly explain the ways as you're hinting above, it would help
me in optimizing my design.
This is my current understanding. Let say we have a four-level FIFO
stack, labelled slots 1-4 from top to bottom. Top of stack is slot 1,
for ease of illustration. Say that the bottom of stack is full and the
remaining three slots are empty. When a new item enters from the top of
the stack, it will have no problem because the top of stack (slot 1) is
empty. Then, the process of fall-through begins.
Since the slot 2 is empty, contents in slot 1 will be copied to slot 2.
Once this is complete (or while it is taking place), slot 1 will be
cleared to make way for the next item to enter the FIFO stack. The same
thing happens when the content moves from slot 2 to slot 3. Since slot
4 is full, the fall-through stops.
Then, here's the process of reading from stack. Slot 4 will be copied
out to output buffer, followed by the slot 4 being cleared. Upon this
occuring, contents in slot 3 will fall-through to slot 4 using the
process as described above.
The problem I'm facing is that I couldn't really figure out the circuit
that can perform just what I've described. Nor am I certain the whole
sequence of events are correct. Is it possible to implement the
fall-through cycle in both synchronous and asychronous (relative to FF
clock)?
Appreciate any input. |
|
| Back to top |
|
|
Del Cecchi
Guest
|
| Posted:
Mon Oct 24, 2005 12:15 am Post subject:
Re: Fall-through stack |
|
|
Faw wrote:
| Quote: | Del Cecchi,
I need the understanding to construct a slightly functionally different
FIFO buffer for my research. So, I needed to know how the fall-through
functionality work. I'll check out 74HC(T)40105 4x16 FIFO datasheet
recommended by Karl Olsen below (Thanks Karl!). But in the meantime, if
you can briefly explain the ways as you're hinting above, it would help
me in optimizing my design.
This is my current understanding. Let say we have a four-level FIFO
stack, labelled slots 1-4 from top to bottom. Top of stack is slot 1,
for ease of illustration. Say that the bottom of stack is full and the
remaining three slots are empty. When a new item enters from the top of
the stack, it will have no problem because the top of stack (slot 1) is
empty. Then, the process of fall-through begins.
Since the slot 2 is empty, contents in slot 1 will be copied to slot 2.
Once this is complete (or while it is taking place), slot 1 will be
cleared to make way for the next item to enter the FIFO stack. The same
thing happens when the content moves from slot 2 to slot 3. Since slot
4 is full, the fall-through stops.
Then, here's the process of reading from stack. Slot 4 will be copied
out to output buffer, followed by the slot 4 being cleared. Upon this
occuring, contents in slot 3 will fall-through to slot 4 using the
process as described above.
The problem I'm facing is that I couldn't really figure out the circuit
that can perform just what I've described. Nor am I certain the whole
sequence of events are correct. Is it possible to implement the
fall-through cycle in both synchronous and asychronous (relative to FF
clock)?
Appreciate any input.
|
As I see it there are two ways of doing this
First way is to have several registers in series and the data ripples to
the bottom, along with a control bit to indicate data or no data. So if
data on the left is valid and the data on the right is not, shift or
flush to the right. reading makes the data read invalid.
A more modern way is a two port ram used as a circular buffer with a
collision detector on the read and write pointers. But that doesn't
have a fall through time, and takes more logic gates.
Just think about the problem and how a latch like a polarity hold works.
del
PS this better not be homework or my reputation will be shot.
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.” |
|
| Back to top |
|
|
Faw
Guest
|
| Posted:
Tue Oct 25, 2005 8:15 am Post subject:
Re: Fall-through stack |
|
|
The datasheet of 74HC(T)40105 is a very helpful reference indeed. It
provides the schematic for the fall-through stack operation. Btw, the
implementation illustrated by Fig.5 in the datasheet is an asynchronous
one, which should reduce the fall-through latency of the stack. Well, I
have yet to simulate the circuit to see the actual operation and
performance of the circuit.
Del, the two-port ram implementation is good for speed, but not so kind
on the gate count. My utmost concern is on the gate count...but of
course speed also matters, so I will look further at the implementation
using the serial registers. Don't worry...it's not for homework.
Fawnizu
PS-Now I wonder why I didn't use this newsgroup during my undergrad
life to solve those tough problems from tough professors. |
|
| Back to top |
|
|
Faw
Guest
|
| Posted:
Tue Oct 25, 2005 4:15 pm Post subject:
Re: Fall-through stack |
|
|
Karl (or anybody),
Since you've seen the datasheet for the 74HC(T)40105, maybe you can
help a little bit about the Fig.5 on page 6. Each of the LATCHES have
two inputs called CL_bar and CL respectively. What are those? And what
do they mean by LATCHES?
Btw, in this document, do they refer to edge-triggered device as latch
and level sensitive with S,R inputs as flip-flop? When I learned it, it
was the other way around. Or is it something different?
Fawnizu |
|
| Back to top |
|
|
|
|
|
|
FAQ
Memberlist
Register
Profile
Log in to check your private messages
Log in