| Author |
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mawcowboy
Guest
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 Posted:
Sun Oct 30, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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Almost all of these questions have been answered, directly or
indirectly, through the messages I have written in various news groups,
simply perform a Google message options function of 'find messages by
author',
here is a link for simplicity's sake,
http://groups.google.com/groups?num=100&hl=en&lr=&ie=ISO-8859-1&scoring=d&q=dolphinconsultant+OR+mawcowboy+OR+cpu16x1832
You must ahve missthe the original post of this thread, however, in
very brief synopsis:
1) I wrote a letter to Washington in 1996 about a computer chip formula
for a very simply but powerful chip DESIGN, VLIW SMP MPP FORTH, I
recieved a 'personal' not interested vote from Microsoft Chairman Bill
Gates.
2) After feeling some pressure to 'continue to give away my idea to the
public', I wrote more letters to the same Washington people, telling
more about the theory and design ( and hoping they would stop riding my
ass), hundreds of pages of documentation where either email or faxed.
3) in the year 2000, Mr. Chuck Moore published information about his
25X work on the internet, I DISCOVERED his information and applied my
knowledge to form a hybrid chip design, Drum roll, please ...
URL,
http://groups.google.com/group/comp.lang.java.machine/msg/b400d03ddc0f5a4f?dmode=source&hl=en
RE,
---
Path:
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From: Geoff <g...@invalid.invalid>
Newsgroups:
comp.lang.java.machine,comp.arch,comp.lang.forth,sci.math,sci.electronics.design
Subject: Re: A stupid post about Intel's latest computer chip ( s)
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On 28 Oct 2005 17:26:51 -0700, "A Man Masterbating Alone In The
Wilderness"
<cpu16x1...@wmconnect.com> wrote:
| Quote: |
Going where no gamer has gone before ... super scalable multiple
parallel symetric parallel processors ( with LEGO(tm) like
expandability,) executing multi layered sprites and partion trees to
drive more ultra hi resolution projection panels, and, so blindingly
fast , a super computer beyond which no mere mortal could hope to
survive.
|
OK, I'll bite. I see post and reposts of this incoherent blather going
back
4 or 5 years, maybe more. I will put it in a form that can't possibly
be
any more clear. I expect you can insert your answers in line.
Suppose I wanted to build a system based on this chip, where do I buy
them,
how much do they cost?
Who fabricates them now, today?
Where can I buy a single-processor development kit?
What is the power consumption?
Where are the performance specifications and timing diagrams?
How is it interfaced to memory?
What are power supply and voltage requirements?
What are the pinouts?
Where's the data sheet?
What compilers are available for it?
Who makes them?
Who publishes new words and vocabularies for it?
How is it debugged?
What about realtime applications?
Interrupt services?
If it isn't real, now, here, today, when will it be made real?
Where are the VHDL or other sources for modeling and fabricating these
devices?
What is the web site of the fabricator and how many samples have they
made?
Who are your customers and what systems have they produced based on
this
design? |
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mawcowboy
Guest
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| Posted:
Sun Oct 30, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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Jerry Avins wrote:
| Quote: | A Man Crying Alone In The Wilderness wrote:
...
Registers based architectures pre-date the use of stack based
architectures, so I guess it depends upon what you call modern. Stack
based architectures are, generally, twice as efficient for fabrication
where the goal is maximum circuit utilization.
In what fabrication process?
|
The one that generates the most fortune for you!
| Quote: |
...
Jerry
--
Engineering is the art of making what you want from things you can get.
|
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ |
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Jerry Avins
Guest
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| Posted:
Sun Oct 30, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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|
Eric P. wrote:
| Quote: | The RCA 1802 COSMAC, circa 1975, it was 5V CMOS (4000 series and
TTL compatible), with the power consumption directly proportional
to clock speed. You could stop the clock and draw only uAmps.
The architecture had its own special brand of weirdness.
It had no stack NOR a formal program counter!
|
One register was designated as the data pointer: register 2 by default
and forced by an interrupt. Register 1, IIRC was the default and
interrupt PC. Register 0 was the DMA pointer both in and out, and could
be general purpose. Small programs could jump to a subroutine simply by
naming a new register as PC. The first subroutine instruction passed
control to the main PC, and the last instruction jumped back to the
beginning. When set up, the subroutine PC pointed to the second
instruction. The 1802 had no CALL or RETURN op codes (the 1803 did).
Instead we used call and return subroutines, built as described. The
scheme designated a link register (so a subroutine could fetch immediate
data inlined in the main routine) and used the data pointer register as
a stack pointer. The link register was incremented in each data fetch,
so it pointed to the next instruction upon return. The contents of the
link register when the CALL subroutine was entered was pushed where the
data pointer (default: 3) designated, and restored by the RETURN
subroutine. My designs had four PC registers, main, interrupt, call,
and return. I designated separate interrupt and everything-else data
pointers, so avoiding critical sections. A really sweet machine, id
slow. In many ways, a PDP 11 invoked deja vu.
| Quote: | My memory may be a bit off, but IIRC...
It was 16 bit address, 8 bit data, with an 8 register bank.
There was a Program Counter Pointer (PCPR) register that
indicated which of the general registers was the program counter.
On interrupt, the PCPR was incremented and the next general
register was used as a program counter.
|
No. It was set to 1, I believe.
| Quote: | It was up to the
interrupt routine to save the state as it required and
manipulate the registers and PCPR if it didn't want to use
up all the general registers saving prior program counters.
|
I have a manual somewhere. Does anyone care?
Unless an interrupt is edge triggered, an interrupt must disable itself,
even if not all interrupts. Otherwise, asserting the interrupt would
lock up the machine and quickly overflow the stack.
Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ |
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mawcowboy
Guest
|
| Posted:
Sun Oct 30, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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|
jmfbahciv@aol.com wrote:
| Quote: | In article <1130606965.410081.278220@g14g2000cwa.googlegroups.com>,
"A Man Crying Alone In The Wilderness" <cpu16x1832@wmconnect.com> wrote:
snip
Even if an architecture defines "trap-only" registers, interrupts must
be disabled for interrupt sservice within the architecture to avoid
multi-trap collisions.
I'd consider that [disabling interrupts to handle each
interrupt] to be a big-time design bug. It doesn't deal
with interrupts that have a higher priority; if an interrupt
has a higher priority you have to catch it, not ignore it, let
alone disable it.
snip
/BAH
|
Something you may find interesting, in theory, my current circuit
theory doesn't include an interrupt system, only a /hardwired/ bus
service priority.
Software binding is performed with a bus id not an interrupt service
address, the bus id is /that/ address. ( a thought)
URL,
http://groups.google.com/group/comp.lang.java.machine/msg/b400d03ddc0f5a4f?dmode=source&hl=en
maw |
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Eric P.
Guest
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| Posted:
Sun Oct 30, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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"Eric P." wrote:
| Quote: |
The architecture had its own special brand of weirdness.
It had no stack NOR a formal program counter!
My memory may be a bit off, but IIRC...
It was 16 bit address, 8 bit data, with an 8 register bank.
There was a Program Counter Pointer (PCPR) register that
indicated which of the general registers was the program counter.
On interrupt, the PCPR was incremented and the next general
register was used as a program counter. It was up to the
interrupt routine to save the state as it required and
manipulate the registers and PCPR if it didn't want to use
up all the general registers saving prior program counters.
|
Ah, I found a description of it.
It was a 16 register x 16 bit bank, 8 bit data.
SEP instruction set 4 bit P register pointer to the program counter.
SEX instruction set 4 bit X register pointer to the index register.
On interrupt P and X are copied to the 8 bit T register
and the forced to 1 and 2 respectively.
Nested interrupts required the programmer to save the
old PC and T values before reenabling interrupts.
There was other weirdness like to call a subroutine you load the
new PC address into a register and used SEP to change which register
was the program counter.
Because of low power and radiation hardness, the 1802 was used in
the Voyager, Viking, and Galileo spacecraft and many satallites.
Eric |
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Ken Smith
Guest
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| Posted:
Sun Oct 30, 2005 6:29 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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|
In article <1130535506.872895.130930@g14g2000cwa.googlegroups.com>,
anonymous <cpu16x1832@wmconnect.com> wrote:
| Quote: |
Ken Smith wrote:
[...]
I did re-entrant code on an 1802. You save the caller's address on the
"stack" when the routines starts up.
[...]
I guess the 1802 was without external interrupts,
|
Others have well covered this.
| Quote: | Or a reason they are not as popular ...
|
... IIRC
AddAtoBandPutInC:
LDI low(A)
PLO 6
LDI high(A)
PLH 6
LDI low(B)
PLO 7
LDI high(B)
PLH 7
LDI low(C)
PLO 8
LDI high(C)
PLH 8
LDN 6
SEX 7
ADD
stn 8
16 instructions to get a simple C = A + B done is a big part of why it
isn't in common use today.
The ability to flip back and forth between co-routines by just doing one
instruction was sort of handy. It also made it easier to pass the address
of a subroutine.
--
--
kensmith@rahul.net forging knowledge |
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Dave Thompson
Guest
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| Posted:
Mon Oct 31, 2005 1:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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On Wed, 26 Oct 2005 01:30:48 -0700, glen herrmannsfeldt
<gah@ugcs.caltech.edu> wrote:
| Quote: | David Hopwood wrote:
[newsgroups trimmed]
(snip regarding split stacks)
Does C require a combine stack? It is a common implementation, but
I don't believe it is required.
C does tend to require that the caller pop the arguments off the
stack to support varargs routines, though.
Varargs calls can use a different (less efficient) calling convention.
I said "tends to" for that reason, though I believe it is rare.
As far as I know, K&R C didn't allow the different calling convention,
as the declaration requirements were not as strong.
K&R didn't; standard (ANSI/ISO) C requires that varargs calls be done |
in the scope of a prototype declaration specifying ellipsis.
| Quote: | In any case, the mechanism must exist, at least for declared varargs
routines.
VAX uses a selfdescribing arglist for (conventionally) all calls. I |
don't recall definitely anything else that does -- maybe i432.
Or LISP machines, but anyone who tries (or tried) to put C on them is
obviously insane.
- David.Thompson1 at worldnet.att.net |
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Jerry Avins
Guest
|
| Posted:
Mon Oct 31, 2005 1:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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|
The Ghost In The Machine wrote:
...
| Quote: | Ah, to think that a modern desktop could now probably
simulate the silly thing faster than it could actually
run back then...
|
For sure! Later chips were faster -- I ran one with a 5 MHz clock, but
speed isn't important for a lot of applications. My .22 rifle shoots
bullets at about 1000 ft/sec. One gains a lot of perspective by quoting
execution times in inches.
The precursor COSMAC was called Fred. It was a toy built to run toys.
The architecture's hidden agenda was making it easy to write
interpreters, and the proof-of-concept implementation was in TTL, the
work of one man. Architectures had progressed from five addresses down
to one, and the design was intended to explore the possibilities of a
zero-address machine. It was the only prototype in the house when RCA
decided that they needed to come out with a microprocessor, and they ran
with it.
Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ |
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Geoff
Guest
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| Posted:
Mon Oct 31, 2005 1:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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A Forth processor document in the comp.lang.java.machine newsgroup.
Telling.
Even more telling.
http://groups.google.com/group/mn.jobs/browse_frm/thread/1113e9c44adc843f/dede2c27f445f780?lnk=st&q=dolphinconsultant+OR+mawcowboy+OR+cpu16x1832&rnum=38&hl=en#dede2c27f445f780
Doesn't spell check or proof-read his cover letters.
"SUMMARY:
I am an experienced programmer. Also, I define a high gross value for
one dollar. "
Whatever that means.
For those who have not already found the origin of Mark's perpetual
reposts of HTML-ified quoted gobbledygook, here is the link to
decently formatted descriptions of the x18 and other stack processors
and Chuck Moore's original work. (Apparently.)
http://www.forthfreak.net/index.cgi?ForthCPUs
And the 25X: http://www.forthfreak.net/misc/25x.pdf (Incomplete?)
The content of Mark's posts can be found here, properly formatted and
readable.
http://www.forthfreak.net/misc/x18.html Tada! Mark, the fact you
couldn't find this or post it in your reply to me tells me how good
your research is.
I call the reader's attention to opcode 14. Called "or" it is
documented as "Exclusive-or S to T". Is it OR or XOR? If XOR, where is
the OR instruction? If it is OR then lacking XOR the processor would
not lend itself to modern day cryptography or graphics processing
where 2400 Mips would prove itself useful. Of course it's always
necessary to have the all-important NOP instruction in a 2400 Mips
processor (instruction 1E). We can do "nothing" really, really fast.
Why aren't OR, AND and XOR all implemented in this processor and the
NOP discarded? Why is a NOP instruction even included in a processor
of this type or any modern HLL such as Forth? Surely we aren't doing
timing loops with NOP instructions in the 21st century. How would a
NOP instruction benefit the design of a processor that has no clock? I
am no Forth programmer, but it seems strange to claim "27 instructions
ideally suited to Forth" where XOR is a primitive word, but to have no
hardware instruction for it. I would also point out that 2^5 is 32 and
the Moore document is 5 opcodes short of a full deck. The following
opcodes are not documented in the Moore description of the x18 core:
04,05,07,0E,16. I submit the Moore document is flawed, incomplete, and
insufficient for a basis of design of a real processor or for
selection of that processor, if it exists, for use in a system. All
this noise is the merest sketch of a processor. If it were the basic
documentation of a real design, that design is suspect.
I repeat and amplify my question:
Where is the source code to the X18 and the 25x?
It would also appear that even Chuck Moore has given up on the 25x:
http://www.colorforth.com/ since the link to the 25x document is
invalid and his status report states: Awaiting funding.
The Forth primitive words:
http://web.archive.org/web/20010828144141/www.cs.cmu.edu/~koopman/stack_computers/appb.html
The Forth instruction frequencies of occurrence:
http://web.archive.org/web/20010828145026/www.cs.cmu.edu/~koopman/stack_computers/appc.html
(I call your attention to the fact that NOOP or NOP is not even
listed.)
The b16 processor was more completely and accurately documented and it
has XOR, COMpliment, AND, OR and two NOP instructions.
http://www.jwdt.com/~paysan/b16.html
Mark, you sound like a really smart and zealous guy, who has
determined he has a mission to realize a stack processor design and
bring it before the world. Your 1999 resumé would _not_ get you a job
working for me. Nevertheless, if you somehow ended up working for me I
would keep you as far as possible from my customers, preferably
sequestered in a lab or a cubicle where you could work on projects
that could be transferred to and realized by a design team who knows
how to document IP and write decently so others can understand the
final product. I would not trust code written by you unless I could
see for myself how well commented and implemented it was, your written
work is sloppy and incomplete though voluminous. I expect your code is
the same. |
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The Ghost In The Machine
Guest
|
| Posted:
Mon Oct 31, 2005 1:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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|
In sci.math, Ken Smith
<kensmith@green.rahul.net>
wrote
on Sun, 30 Oct 2005 18:29:05 +0000 (UTC)
<dk33dh$rqt$5@blue.rahul.net>:
| Quote: | In article <1130535506.872895.130930@g14g2000cwa.googlegroups.com>,
anonymous <cpu16x1832@wmconnect.com> wrote:
Ken Smith wrote:
[...]
I did re-entrant code on an 1802. You save the caller's address on the
"stack" when the routines starts up.
[...]
I guess the 1802 was without external interrupts,
Others have well covered this.
Or a reason they are not as popular ...
.. IIRC
AddAtoBandPutInC:
LDI low(A)
PLO 6
LDI high(A)
PLH 6
LDI low(B)
PLO 7
LDI high(B)
PLH 7
LDI low(C)
PLO 8
LDI high(C)
PLH 8
LDN 6
SEX 7
ADD
stn 8
16 instructions to get a simple C = A + B done is a big part of why it
isn't in common use today.
The ability to flip back and forth between co-routines by just doing one
instruction was sort of handy. It also made it easier to pass the address
of a subroutine.
|
Yeah, but if it takes 32 cycles to do the equivalent of
ADD3B M1,M2,R0
(which e.g. the VAX could do easily enough), with each
cycle taking half a microsecond, it's not exactly the
fastest beastie in the world, though it was easy to play
with back then; it didn't really need all that much in
the way of support beyond a basic crystal oscillator. :-)
Ah, to think that a modern desktop could now probably
simulate the silly thing faster than it could actually
run back then...
--
#191, ewill3@earthlink.net
It's still legal to go .sigless. |
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Jerry Avins
Guest
|
| Posted:
Mon Oct 31, 2005 1:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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|
Ken Smith wrote:
| Quote: | In article <1130535506.872895.130930@g14g2000cwa.googlegroups.com>,
anonymous <cpu16x1832@wmconnect.com> wrote:
Ken Smith wrote:
[...]
I did re-entrant code on an 1802. You save the caller's address on the
"stack" when the routines starts up.
[...]
I guess the 1802 was without external interrupts,
Others have well covered this.
Or a reason they are not as popular ...
.. IIRC
AddAtoBandPutInC:
LDI low(A)
PLO 6
LDI high(A)
PLH 6
LDI low(B)
PLO 7
LDI high(B)
PLH 7
LDI low(C)
PLO 8
LDI high(C)
PLH 8
LDN 6
SEX 7
ADD
stn 8
16 instructions to get a simple C = A + B done is a big part of why it
isn't in common use today.
|
What's more, each instruction cycle took 8 clock cycles. With a 1 MHz
clock, that seems slow, but on one machine I built that controlled and
gathered data from an Auger spectrometer, averaging thousands of
readings and passing the results to a minicomputer when the run was
over, I slowed the clock to 250 KHz to assure robustness in the presence
of noise.
| Quote: | The ability to flip back and forth between co-routines by just doing one
instruction was sort of handy. It also made it easier to pass the address
of a subroutine.
|
A real honey, for my part.
Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ |
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Oliver S.
Guest
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| Posted:
Mon Oct 31, 2005 8:38 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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| Quote: | Post-script, Lego Mindstorms, Open Firmware...
...
No need to maintain if it does the job already
|
Ok, then this thing is good for single-developer-projects,
i.e. will fail on most other projects. |
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Oliver S.
Guest
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| Posted:
Mon Oct 31, 2005 8:44 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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It's a common mistake of some IT-geeks that once they understood
something new, they think it's the best idea since sliced bread. |
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Oliver S.
Guest
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| Posted:
Mon Oct 31, 2005 8:49 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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| Quote: | Varargs calls can use a different (less efficient) calling convention.
|
But they're used rather almost never on performance-critical functions.
So if your objection was to note that this ineffitiency might be a pro-
blem: it isn't. |
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Oliver S.
Guest
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| Posted:
Mon Oct 31, 2005 8:53 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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| Quote: | Forth-style model, separating the return stack from the data stack
allows much shallower stacks than a C-style stack frame requires.
i don't see how this affects the space needed for a stack.
it's just partitioned.
Does C require a combine stack? It is a common implementation, but
I don't believe it is required.
no. in fact, the return address can be passed in a register.
as for FORTH, doesn't it require two memory fetches for each interpreter
cycle?
|
Sorry, but can you please place your FUps to the place they belong?
Why do you FUp to an article some rounds below that article you're
commenting? This is plainly idiotic. |
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