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Oliver S.
Guest
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 Posted:
Mon Oct 31, 2005 8:56 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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| Quote: | I don't know about what would be involved either, but wouldn't separating
the return address stack from the data stack help to prevent some security
flaws as it would be harder to use an "oversize" piece of data to overwrite
the return address and force execution of rogue code?
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Of course, but I think that's not the way to solve this problem.
The better way would be to use more robust languages instad of this silly C. |
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A Man Crying Alone In The
Guest
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| Posted:
Mon Oct 31, 2005 9:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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HO HO HE HE , thanks for the nice things said , in a twist of words
sort of way, but I got to go to bed , The news tonight talks about a
deer that jumped into the front seat of a womans vehicle, an eight
point buck in Farmington Minnesota, ... but I got protypes to layout
for operating laser cutter mill, special setups, NC macro tool building
fun, 1/3 my previous earnings, no health, etc. ( no way!), but anyway.
.... What /was/ your clearance? FBI, surely not CIA or NSA, plus close
ties with coporate? I don't need this shit anymore!
Path:
g2news1.google.com!news4.google.com!news3.google.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!trnddc02.POSTED!befad20c!not-for-mail
From: Geoff <g...@invalid.invalid>
Newsgroups:
comp.lang.java.machine,comp.arch,comp.lang.forth,sci.math,sci.electronics.design
Subject: Re: A stupid post about Intel's latest computer chip ( s)
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A Forth processor document in the comp.lang.java.machine newsgroup.
Telling.
Even more telling.
http://groups.google.com/group/mn.jobs/browse_frm/thread/1113e9c44adc843f/dede2c27f445f780?lnk=st&q=dolphinconsultant+OR+mawcowboy+OR+cpu16x1832&rnum=38&hl=en#dede2c27f445f780
Doesn't spell check or proof-read his cover letters.
"SUMMARY:
I am an experienced programmer. Also, I define a high gross value for
one dollar. "
Whatever that means.
For those who have not already found the origin of Mark's perpetual
reposts of HTML-ified quoted gobbledygook, here is the link to
decently formatted descriptions of the x18 and other stack processors
and Chuck Moore's original work. (Apparently.)
http://www.forthfreak.net/index.cgi?ForthCPUs
And the 25X: http://www.forthfreak.net/misc/25x.pdf (Incomplete?)
The content of Mark's posts can be found here, properly formatted and
readable.
http://www.forthfreak.net/misc/x18.html Tada! Mark, the fact you
couldn't find this or post it in your reply to me tells me how good
your research is.
I call the reader's attention to opcode 14. Called "or" it is
documented as "Exclusive-or S to T". Is it OR or XOR? If XOR, where is
the OR instruction? If it is OR then lacking XOR the processor would
not lend itself to modern day cryptography or graphics processing
where 2400 Mips would prove itself useful. Of course it's always
necessary to have the all-important NOP instruction in a 2400 Mips
processor (instruction 1E). We can do "nothing" really, really fast.
Why aren't OR, AND and XOR all implemented in this processor and the
NOP discarded? Why is a NOP instruction even included in a processor
of this type or any modern HLL such as Forth? Surely we aren't doing
timing loops with NOP instructions in the 21st century. How would a
NOP instruction benefit the design of a processor that has no clock? I
am no Forth programmer, but it seems strange to claim "27 instructions
ideally suited to Forth" where XOR is a primitive word, but to have no
hardware instruction for it. I would also point out that 2^5 is 32 and
the Moore document is 5 opcodes short of a full deck. The following
opcodes are not documented in the Moore description of the x18 core:
04,05,07,0E,16. I submit the Moore document is flawed, incomplete, and
insufficient for a basis of design of a real processor or for
selection of that processor, if it exists, for use in a system. All
this noise is the merest sketch of a processor. If it were the basic
documentation of a real design, that design is suspect.
I repeat and amplify my question:
Where is the source code to the X18 and the 25x?
It would also appear that even Chuck Moore has given up on the 25x:
http://www.colorforth.com/ since the link to the 25x document is
invalid and his status report states: Awaiting funding.
The Forth primitive words:
http://web.archive.org/web/20010828144141/www.cs.cmu.edu/~koopman/stack_computers/appb.html
The Forth instruction frequencies of occurrence:
http://web.archive.org/web/20010828145026/www.cs.cmu.edu/~koopman/stack_computers/appc.html
(I call your attention to the fact that NOOP or NOP is not even
listed.)
The b16 processor was more completely and accurately documented and it
has XOR, COMpliment, AND, OR and two NOP instructions.
http://www.jwdt.com/~paysan/b16.html
Mark, you sound like a really smart and zealous guy, who has
determined he has a mission to realize a stack processor design and
bring it before the world. Your 1999 resumé would _not_ get you a job
working for me. Nevertheless, if you somehow ended up working for me I
would keep you as far as possible from my customers, preferably
sequestered in a lab or a cubicle where you could work on projects
that could be transferred to and realized by a design team who knows
how to document IP and write decently so others can understand the
final product. I would not trust code written by you unless I could
see for myself how well commented and implemented it was, your written
work is sloppy and incomplete though voluminous. I expect your code is
the same. |
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A Man Crying Alone In The
Guest
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| Posted:
Mon Oct 31, 2005 9:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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| Please deacronymize. This is plainly rude. |
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A Man Crying Alone In The
Guest
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| Posted:
Mon Oct 31, 2005 9:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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Although some people consider a spam bot totally inappropriate, I for
one, enjoy an occasional curve ball; however, label from /bot-xyz/,
appropriately, maybe, in my view. |
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A Man Crying Alone In The
Guest
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| Posted:
Mon Oct 31, 2005 9:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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An obvious strawman for some idiotic C v.s all contenders flame/war,
( A "spam bot" robotic hook, is another, guess ) |
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A Man Crying Alone In The
Guest
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| Posted:
Mon Oct 31, 2005 9:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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An obvious strawman for some idiotic C v.s all contenders flame/war,
( A "spam bot" robotic hook, is another, guess ) |
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Jan Vorbrüggen
Guest
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| Posted:
Mon Oct 31, 2005 9:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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| Quote: | I have a manual somewhere. Does anyone care?
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There must be some people at JPL that do, insofar that, IIRC, 1802s run
the Voyagers, and they're still out there talking to JPL...
Jan |
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Guest
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| Posted:
Mon Oct 31, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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In article <4364E1B3.7FB9FBB6@sympaticoREMOVE.ca>,
"Eric P." <eric_pattison@sympaticoREMOVE.ca> wrote:
| Quote: | jmfbahciv@aol.com wrote:
In article <1130606965.410081.278220@g14g2000cwa.googlegroups.com>,
"A Man Crying Alone In The Wilderness" <cpu16x1832@wmconnect.com> wrote:
snip
Even if an architecture defines "trap-only" registers, interrupts must
be disabled for interrupt sservice within the architecture to avoid
multi-trap collisions.
I'd consider that [disabling interrupts to handle each
interrupt] to be a big-time design bug. It doesn't deal
with interrupts that have a higher priority; if an interrupt
has a higher priority you have to catch it, not ignore it, let
alone disable it.
Let me try that again
It seems accidental CarriageReturn = SendMessageNow.
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What idiot implemented that !!!!?
| Quote: |
Some architectures only save one prior level of context.
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I'm assuming you meant priority and not prior. :-)
| Quote: | E.g. a RISC processor would just copy the old program counter
and processor status value into a specific register pair,
disable interrupts and jam the interrupt address into the PC.
The interrupt routine preamble saves the prior state and reenables.
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But this routine cannot be very long at all.
| Quote: |
The RCA 1802 COSMAC, circa 1975, it was 5V CMOS (4000 series and
TTL compatible), with the power consumption directly proportional
to clock speed. You could stop the clock and draw only uAmps.
The architecture had its own special brand of weirdness.
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I think every architecture has one or two plus a couple that
are unknown.
| Quote: | It had no stack NOR a formal program counter!
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<grin> You might try to take a look at IBM 1620.
| Quote: | My memory may be a bit off, but IIRC...
It was 16 bit address, 8 bit data, with an 8 register bank.
There was a Program Counter Pointer (PCPR) register that
indicated which of the general registers was the program counter.
On interrupt, the PCPR was incremented and the next general
register was used as a program counter. It was up to the
interrupt routine to save the state as it required and
manipulate the registers and PCPR if it didn't want to use
up all the general registers saving prior program counters.
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You are way out of my realm of expertise. :-) That's Ok.
Have you built a breadboard yet based on your design?
Hook it up to a coffee pot, then a keyboard, or a remote
control. hmm...or have the remote control drive it.
/BAH |
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Jerry Avins
Guest
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| Posted:
Mon Oct 31, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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Oliver S. wrote:
| Quote: | It's a common mistake of some IT-geeks that once they understood
something new, they think it's the best idea since sliced bread.
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Sliced bread stales too fast. I leave my loaves whole and slice as
needed. Thick slices for toast and thin for sandwiches. What's this
one-size-fits-all nonsense? So what?
Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ |
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Eric P.
Guest
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| Posted:
Mon Oct 31, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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jmfbahciv@aol.com wrote:
| Quote: |
In article <4364E1B3.7FB9FBB6@sympaticoREMOVE.ca>,
"Eric P." <eric_pattison@sympaticoREMOVE.ca> wrote:
Some architectures only save one prior level of context.
I'm assuming you meant priority and not prior. :-)
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Prior could be a lower priority context too.
| Quote: | E.g. a RISC processor would just copy the old program counter
and processor status value into a specific register pair,
disable interrupts and jam the interrupt address into the PC.
The interrupt routine preamble saves the prior state and reenables.
But this routine cannot be very long at all.
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It only takes a dozen or so instructions to save the prior context.
On a modern high speed RISC processor that is nothing, and the
flexibility may be worthwhile compared to hardwired approaches.
In the older midframe machines with much slower clocks there was a
significant advantage to having much of this done in the hardware.
But the microprocessors of the 1975..1980 era were extremely gate
challenged so they tending to be fairly RISC-like in their approach.
The 8008/8080 didn't even handle fully interrupts itself.
The interrupt controller jammed a CALL instruction onto the bus
(and x86 probably still has compatibility modes that do so today).
| Quote: | The RCA 1802 COSMAC, circa 1975, it was 5V CMOS (4000 series and
TTL compatible), with the power consumption directly proportional
to clock speed. You could stop the clock and draw only uAmps.
The architecture had its own special brand of weirdness.
I think every architecture has one or two plus a couple that
are unknown.
It had no stack NOR a formal program counter!
grin> You might try to take a look at IBM 1620.
My memory may be a bit off, but IIRC...
It was 16 bit address, 8 bit data, with an 8 register bank.
There was a Program Counter Pointer (PCPR) register that
indicated which of the general registers was the program counter.
On interrupt, the PCPR was incremented and the next general
register was used as a program counter. It was up to the
interrupt routine to save the state as it required and
manipulate the registers and PCPR if it didn't want to use
up all the general registers saving prior program counters.
You are way out of my realm of expertise. :-) That's Ok.
Have you built a breadboard yet based on your design?
Hook it up to a coffee pot, then a keyboard, or a remote
control. hmm...or have the remote control drive it.
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We can only hope that when Vger shows up, looking for its' creator,
that it is not mighty pissed at what we did to it.
Groups trimmed.
Eric |
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Pig Bladder
Guest
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| Posted:
Mon Oct 31, 2005 5:15 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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On Sun, 30 Oct 2005 20:05:38 -0800, A Man Crying Alone In The Wilderness wrote:
| Quote: | Please deacronymize. This is plainly rude.
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It's much ruder to post a naked comment entierly devoid of context.
--
Flap!
The Pig Bladder from Uranus, still waiting for that
hot babe to ask what my favorite planet is. ;-j |
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Ken Smith
Guest
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| Posted:
Tue Nov 01, 2005 1:59 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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In article <zvidnZet0MilufjeRVn-rg@rcn.net>, Jerry Avins <jya@ieee.org> wrote:
[... 1802 ...]
| Quote: | What's more, each instruction cycle took 8 clock cycles. With a 1 MHz
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12 cycles IIRC.
--
--
kensmith@rahul.net forging knowledge |
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Andrew Haley
Guest
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| Posted:
Tue Nov 01, 2005 9:15 am Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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In comp.lang.forth Ken Smith <kensmith@green.rahul.net> wrote:
| Quote: | In article <zvidnZet0MilufjeRVn-rg@rcn.net>, Jerry Avins <jya@ieee.org> wrote:
[... 1802 ...]
What's more, each instruction cycle took 8 clock cycles. With a 1 MHz
12 cycles IIRC.
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I've got the data book here (I never throw anything away!) and a
machine cycle is 8 clock ticks [*]. You may be thinking of the 8051.
Andrew.
[*] However, 1802 instructions took 2 or 3 machine cycles. |
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Ken Smith
Guest
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| Posted:
Tue Nov 01, 2005 3:06 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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In article <11mebbbsht8md85@news.supernews.com>,
Andrew Haley <andrew29@littlepinkcloud.invalid> wrote:
[...]
| Quote: | I've got the data book here (I never throw anything away!) and a
machine cycle is 8 clock ticks [*]. You may be thinking of the 8051.
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Yes, I suspect so.
| Quote: | [*] However, 1802 instructions took 2 or 3 machine cycles.
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That could be why I though 8 was quick.
A few weeks back, I went looking for some of my source code on the 1802.
I couldn't find it. I do remember that the 64bit/32bit->32bit divide
took, near enough, forever.
--
--
kensmith@rahul.net forging knowledge |
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glen herrmannsfeldt
Guest
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| Posted:
Thu Nov 10, 2005 4:14 pm Post subject:
Re: A stupid post about Intel's latest computer chip ( s) |
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Ken Smith wrote:
| Quote: | In article <11mebbbsht8md85@news.supernews.com>,
Andrew Haley <andrew29@littlepinkcloud.invalid> wrote:
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(snip)
| Quote: | [*] However, 1802 instructions took 2 or 3 machine cycles.
|
ICT, the Integer Cosine Transform, was specifically designed to
minimize the 1 bits in the coefficients for a processor without
multiply such as the CDP1802.
The reference is somewhere in jpl.gov.
-- glen |
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