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Rupert Pigott · Guest

Anyone else somewhat gobsmacked by the SPECfp/Watt *per socket*
that the Inquirer claims for the PA Semi chip ? Specifically ~2000
SPECfp per core, two cores per chip. PA Semi claim 5-13W power
consumption for a chip. That appears to include a whole chunk of
stuff like PCIe and 10GigE ports too...

Cigarette packet math indicates that is roughly a factor of 10
improvement over the current high-end cores as far as FLOPS/Watts
goes. Pretty bold claims, it will be interesting to see what the
silicon actually does. If it comes up to scratch I wouldn't be
surprised to see those things getting slotted into a BG/L chassis.

Anyone smelling rats or are you guys quiet because you're checking
your grapevines ? :)

Cheers,
Rupert

Felger Carbon · Guest

"Rupert Pigott" <darkboong@hotmail.com> wrote in message
news:1130282261.517707.241570@g14g2000cwa.googlegroups.com...

Jason Lee Eckhardt · Guest

In article <1130282261.517707.241570@g14g2000cwa.googlegroups.com>,
Rupert Pigott <darkboong@hotmail.com> wrote:

Greg Lindahl · Guest

In article <1130282261.517707.241570@g14g2000cwa.googlegroups.com>,
Rupert Pigott <darkboong@hotmail.com> wrote:

John Mashey · Guest

Greg Lindahl wrote:

Rupert Pigott · Guest

Felger Carbon wrote:

Rupert Pigott · Guest

Greg Lindahl wrote:

Niels Jørgen Kruse · Guest

Rupert Pigott <darkboong@hotmail.com> wrote:

Joe Seigh · Guest

Rupert Pigott wrote:

Iain McClatchie · Guest

Rupert> Anyone else somewhat gobsmacked by the SPECfp/Watt *per
Rupert> socket*

Yep, but somewhat less gobsmacked by the SpecInt2000 per core
("> 1000"). The Pentium M at 2260 MHz gets 1812, that's roughly
the same frequency, screwier instruction set, similar power
dissipation, shipping now.

I was at MPF yesterday, and I think they said they were on
TSMC 65nm, in which case 2 GHz is roughly a 20 inverter-3 delay
machine. The Pentium M has the advantage of running on a much
faster process, which explains the MHz advantage, but not the
per-MHz advantage.

My guess is that the per-MHz advantage comes from better branch
prediction, maybe better hardware memory prefetch prediction,
and definitely a closer L2 cache. This last issue is quite
curious.

On a dual-core Athlon, each core has it's own L2. The good
thing here is that, since there is no crossbar to cross (no
arbitration), the latency is lower. The annoying bit is that
half the L2 is on the other side of the crossbar (and you take
a miss latency before you see it) and that coherency is more
difficult. Despite longer latency to half the L2, the lower
latency to the half used more often is still better
performance. I doubt it would give them the extra 300
SpecInt2000, but it's probably a strong effect (I'd expect
more than 50 SpecInt2000).

So why didn't they do seperate L2s? It might be a power issue.
To check for a hit in the caches, you have to check both of
their tags. Checking two caches instead of one is sort of
like checking a 4-way associative cache instead of a 2-way.
Tag fetch width doubles, but the bit line loading on each
drops, so the power goes up, um, less than double. Hmm...
Here's a clue: in their presentation, Jim Keller said they
chose 2-way associative caches over 4-way as a tradeoff to
get less power.

The interesting thing here is that more associativity doesn't
*have* to cost more power. If you can predict which way is
most likely to hit, you can check the ways serially, and save
power that way. This works if the prediction is free. Free
predictions are available for most of the PA-Semi design
though. In the case of a core, it's most likely to hit in
the half of the L2 that it fills. In the case of an I/O,
it's most likely to hit in the same side of the L2 that the
I/O stream hit last time.

The more I think about this thing, the more I think AMD has
to get a better core done before Intel ships a Pentium M
with an integrated memory controller into the desktop market.

Iain McClatchie · Guest

Iain> (I'd expect more than 50 SpecInt2000).

Hmph. A little more calculation and I got 0.07 CPI for their 22-cycle
L2, and a 1.0 CPI overall to make 1000 SpecInt2000. So if they could
shave 8 cycles by avoiding the crossbar, they'd see a 0.025 CPI
improvement, good for an extra 25 SpecInt2000, or about half what I
was guessing above.

David Kanter · Guest

Joe Seigh wrote:

Andrew Reilly · Guest

On Wed, 26 Oct 2005 21:02:03 -0700, David Kanter wrote:

Anton Ertl · Guest

Andrew Reilly <andrew-newspost@areilly.bpc-users.org> writes:

Niels Jørgen Kruse · Guest

Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:

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