DonQuixote
Joined: 23 Aug 2005
Posts: 3
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 Posted:
Sat Oct 29, 2005 1:43 am Post subject:
Architecture which accesses registers as a circular queue |
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Hi folks: 
I wanted to post some links to information about an innovative architecture out of Japan which seems to solve some of the problems of Instruction Level Parallelism with a simple and elegant hardware design.
Rather than accessing registers randomly (as in RISC, CISC, VLIW, etc) or as a stack (as in JAVA or FORTH based chips)... the instructions read operands off the head of a queue and write the results to the tail. Because every write is to a new entry in the queue, the effect is that Write After Write (WAW) and Write After Read (WAR) hazards are eliminated. Read After Write (RAW) hazards occur when a long latency instruction such as Load or Divide has not yet produced the data required by a subsequent instruction. These situations cause a pipeline stall on the instruction in question, but other instructions may proceed to completion in parallel.
The architecture allows good ILP because the queue can be loaded up with operands and then instructions can be executed in parallel, reading and writing data from different segments of the queue simultaneously. The hardware makes sure that the operand queue is always in the order that results are produced.
The Architecture has several advantages:
1. Does not need special hardware to keep track of Out of Order instructions and register renaming.
2. Does not requre complex complilers as in VLIW.
3. Significantly smaller code size to RISC and VLIW.
4. Software does not need to be optimized or recompiled from one generation of hardware to the next.
Hardware features such as the number of execution units, number of registers, number of threads are hidden from the software. (Note the proposal at the website below does not speak of a multithreaded version, but the architecture lends itself well to sharing of execution units by multiple threads, each of which have thier ow register queue.
We can discuss the specifics more later. Please take a look at the flowwing links and let me know what you think.
1. Home page:
http://www.sowa.is.uec.ac.jp/
2. Introduction to concept of queued registers
http://www.sowa.is.uec.ac.jp/sowalab/PQPproject-efr.html
3. Overview of ISA and how ILP is defined from data flow diagrams.
http://www.sowa.is.uec.ac.jp/sowalab/fpga/doc/ipsj2004_markov.pdf
4. Some hardware details including pipeline stages.
http://www2.sowa.is.uec.ac.jp/~ben/publications/sll020405.pdf
5. More details on ISA
http://www.sowa.is.uec.ac.jp/sowalab/fpga/private/instructions_set_architecture.html#2.1.3
6. Links to more documentation:
http://www.sowa.is.uec.ac.jp/sowalab/fpga/
Enjoy. I hope to get a good discussion on this architecture.
Regards,
Tom |
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