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what is the need for two levels of cache, L1 and L2?
thanks
-harshal

but what is the need of two separate cache, why cant we have just one?

Because if some isn't as ingenious as HP,
caches can't be fast *and* large. *g*

Terje Mathisen <terje.mathisen@hda.hydro.com> writes:

Patrick, you shouldn't confuse a poor student like that!

Oh. Sorry. Matter is complex.

In reality L1 and L2 caches exists for redundancy/recovery purposes:

If there is an error in one of them, the other can take over, the 1/2
designations are really just to tell which cache will wake up as the
primary, and which one is the backup.

Clear?

But, that would only work on something like Intels processors with
inclusive cache organization. On AMD processors with exclusive
L1 and L2 caches, it cannot be possible.

Maybe Intel can get away with parity protecting the caches,
and AMD must use ECC throughout? I remember IBM write
interesting things about that in some research papers.

best regards
Patrick

"Oliver S." <Follow.Me@gmx.net> writes:

... HP holds a patent on fast+large combined caches, and nobody wants to pay for that.

Interesting! Can you give some links on that?

I think maybe I could have read that in an earlier homework thread,
some years ago...

So everybody but HP uses a fast but small L1 cache, and a large but slow L2 cache.

Is this the reason for the PA-RISC CPUs to have such hughe L1-caches?

Well, I think that it all depends on what CPU designers know about
the codes that will run on their CPUs, and which cache design is
thought most useful performance/whateverwise for that set of codes.

So, what I would like to know, is what was the nature of the codes
which made HP chose a unified and huge L1 cache for a range of their
PA-RISC processors.

best regards
Patrick

Patrick Schaaf wrote:

harshal38@gmail.com writes:


what is the need for two levels of cache, L1 and L2?


Comparing L1 and L2 cache to each other, note that one is fast,
and the other is large. HP holds a patent on fast+large combined
caches, and nobody wants to pay for that. So everybody but HP
uses a fast but small L1 cache, and a large but slow L2 cache.

Same result, less royalties.

Patrick, you shouldn't confuse a poor student like that!

In reality L1 and L2 caches exists for redundancy/recovery purposes:

If there is an error in one of them, the other can take over, the 1/2
designations are really just to tell which cache will wake up as the
primary, and which one is the backup.

Clear?

Terje
--
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

harshal38@gmail.com writes:

what is the need for two levels of cache, L1 and L2?

Comparing L1 and L2 cache to each other, note that one is fast,
and the other is large. HP holds a patent on fast+large combined
caches, and nobody wants to pay for that. So everybody but HP
uses a fast but small L1 cache, and a large but slow L2 cache.

Same result, less royalties.

best regards
Patrick

... HP holds a patent on fast+large combined caches, and nobody wants to pay for that.

Interesting! Can you give some links on that?

So everybody but HP uses a fast but small L1 cache, and a large but slow L2 cache.

Is this the reason for the PA-RISC CPUs to have such hughe L1-caches?

but what is the need of two separate cache, why cant we have just one?

"Dale Morris" <dale.morris@hp.com> writes:

The PA processors implement a fascinating wave pipelining of the cache,
which allows for fast access despite the size.

I thought that was just for the older ones with the off-chip L1. Did the
PA-8500 and beyond do wave pipelining for the on chip L1 cache?

--
Douglas Siebert dsiebert@excisethis.khamsin.net

Give a man a match, and he'll be warm for a minute. Set him on fire, and
he'll be warm for the rest of his life.

"Patrick Schaaf" <mailer-daemon@bof.de> wrote in message
news:4365d84c$0$25639$9b622d9e@news.freenet.de...

"Oliver S." <Follow.Me@gmx.net> writes:

... HP holds a patent on fast+large combined caches, and nobody wants to
pay for that.

Interesting! Can you give some links on that?

I think maybe I could have read that in an earlier homework thread,
some years ago...

So everybody but HP uses a fast but small L1 cache, and a large but
slow L2 cache.

Is this the reason for the PA-RISC CPUs to have such hughe L1-caches?

Well, I think that it all depends on what CPU designers know about
the codes that will run on their CPUs, and which cache design is
thought most useful performance/whateverwise for that set of codes.

So, what I would like to know, is what was the nature of the codes
which made HP chose a unified and huge L1 cache for a range of their
PA-RISC processors.

Generally speaking, processors have multiple levels of cache to provide some
(small) amount of cache at very low latency, and some (greater) amount of
cache with somewhat longer latency (but still less than memory latency).
This combination tends to yield the lowest average dynamic latency, and
hence the best performance.

Everyone would prefer a large, very-low-latency cache (something with the
latency of L1, but the size of L2), if they could get it. There are two
things that enabled the large single-level cache in PA-RISC:

a) PA-RISC disallows virtual address aliasing to a great degree

More correctly, it tasks the OS with ensuring coherence in the presence of
virtual address aliasing. This means that the cache can be virtually
indexed with no need for HW to do reverse mappings, etc. to detect aliasing.
Hence, we can start looking up in a large cache even before the address has
been translated.

b) Cool design

The PA processors implement a fascinating wave pipelining of the cache,
which allows for fast access despite the size.

Now, the PA design approach was never carried to the multi-GHz range, and in
that range the single large cache approach might not have worked as well,
given that it would have to be multi-cycle.

Hope this helps.

- Dale Morris
Itanium processor architect
Hewlett-Packard Co.

Patrick, you shouldn't confuse a poor student like that!

In reality L1 and L2 caches exists for redundancy/recovery purposes:

If there is an error in one of them, the other can take over, the 1/2
designations are really just to tell which cache will wake up as the
primary, and which one is the backup.

Clear?

Terje

thank you. i got the idea some what, but i still would like to read
more about it

In article <1130743070.293519.32050@f14g2000cwb.googlegroups.com>
harshal38@gmail.com writes:

what is the need for two levels of cache, L1 and L2?
thanks
-harshal

This should be multiple forms of cash.

A credit card may give you access to
large amounts of money, but your purchases will be slowed
as you sign the form and perhaps show identification to the merchant.
If you pay directly, using money (e.g., dollar bills, Euro currency)
from your pocket, individual transactions will be faster but
your capacity is much smaller.


If you are an American tourist in a foreign nation,
you may have access to many US dollars (your home currency)
but access to them will

--
The 2nd John Adams president lost to the winner of the Battle of New Orleans.
The 2nd George Bush president lost the Battle of New Orleans.

pmontgom@cwi.nl Microsoft Research and CWI Home: Bellevue, WA

In article <Ip8yw8.4r7@cwi.nl>, Peter-Lawrence.Montgomery@cwi.nl
says...

In article <1130743070.293519.32050@f14g2000cwb.googlegroups.com
harshal38@gmail.com writes:
what is the need for two levels of cache, L1 and L2?
thanks
-harshal

This should be multiple forms of cash.

A credit card may give you access to
large amounts of money, but your purchases will be slowed
as you sign the form and perhaps show identification to the merchant.
If you pay directly, using money (e.g., dollar bills, Euro currency)
from your pocket, individual transactions will be faster but
your capacity is much smaller.

Good point. This is also why AMD went to a NUMA (Non-Uniform
Monitary Access) architecture. Their processors are made in
Germany, but are a US company, so accessing bank accounts and
varying amounts of money world-wide is important.

If you are an American tourist in a foreign nation,
you may have access to many US dollars (your home currency)
but access to them will

....or an American company in Germany, for instance.

--
Keith

"Peter L. Montgomery" <Peter-Lawrence.Montgomery@cwi.nl> writes:

what is the need for two levels of cache, L1 and L2?

Ignore the other posters, plagiarizing their answers will give you a
lowly C. Plagiarizing my answer, on the other hand, will guarantee
you a uniquely special mark.

Address Equity is the most important reason for having two
caches. This is how it works:

In advanced architectures with two caches, one is designated the C*
and the other is designated the P*

When culturally sensitive algorithms are run, better cache stride
matching is obtained if the caches are dynamically renamed to S* and
S**

Symmetry sharing/breaking schemes with optional temporal reversal
algorithms then permit the generation of irreproducible results.
http://www.jir.com/geographic.html

As an extension of this concept, HP's next generation processor using
temporal coherence will have 7 levels of caches, one for each day of
the week. Depending on the day of the week, one level will be
designated the primary cache ( a.k.a : the designated driver ) and the
other will be the drinkers. This has profound links with the drinking
philosophers problem.


C* : Catholic
P* : Protestant
S* : Shia
S**: Sunni

rambam@bigpond.net.au wrote:

As an extension of this concept, HP's next generation processor using
temporal coherence will have 7 levels of caches, one for each day of
the week. Depending on the day of the week, one level will be
designated the primary cache ( a.k.a : the designated driver ) and the
other will be the drinkers. This has profound links with the drinking
philosophers problem.

Yes, but you just wait for the HP processor that is slated after that -
it makes use of temporal incoherence and keeps the data for all the days
in the same caches, thus being able to get 7x better cache miss ratio.

[sorry for the spoiler, HP folks ;-)]

--
Sander

+++ Out of cheese error +++