Martin Thompson
Guest
|
 Posted:
Fri Nov 04, 2005 5:15 pm Post subject:
Re: Synchronouse dual-port memories implementation or regist |
|
|
sutejok@gmail.com writes:
| Quote: | I was looking at the specification of openRISC 1200 IP Core (from
www.opencores.org).
In the spec (page 11) it says that tge GPRs are implemented as "two
synchronous dual-port memories".
|
I'd guess "Two dual port memories that are synchronous" :-) IE, they
both use the same clock?
I don't know, but reckon they do this to give them two read
ports and one write port (they write the same data into both
memories). Assuming that by dual port they mean "memory that has a
read port and a write port". Xilinx Block RAM has two ports, each
with a read and write port (ir 4 ports in total). This is probably
what they are using for the GPRs.
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt |
|
FAQ
Memberlist
Register
Profile
Log in to check your private messages
Log in