| Author |
Message |
Dom Gilligan
Guest
|
 Posted:
Fri Nov 04, 2005 5:15 pm Post subject:
Opcode size < instruction memory word size? |
|
|
I'm writing a simulator and am wondering about supporting
architectures where a fixed-length opcode is smaller than the
instruction memory width - for example, a 12-bit opcode, but a 16-bit
memory.
I've got a vague recollection that there's an Analog Devices DSP that
does this. Does anyone know if this is the case, or if there are other
processors that do this? Presumably these processors (if they exist)
have word-addressable instruction memory and can't access the unused
bits for opcode fetches, but does anyone know of a byte-addressable
example, where the opcodes fit into memory with no unused bits?
Thanks -
Dom |
|
| Back to top |
|
 |
Guest
|
| Posted:
Fri Nov 04, 2005 5:15 pm Post subject:
Re: Opcode size < instruction memory word size? |
|
|
Why not just put some kind of buffer between the inbound instructions
from memory and the consuming side of the decoder. 2 to 4 entries
should be sufficient. With a big multiplexor between the buffer and the
decoder, byte level or nibble level or bit level or anything in between
is doable. You just have to figgure out how fast you can look at a bit
field and compute the length of that instruction. |
|
| Back to top |
|
|
Dom Gilligan
Guest
|
| Posted:
Fri Nov 04, 2005 5:15 pm Post subject:
Re: Opcode size < instruction memory word size? |
|
|
On 4 Nov 2005 07:10:27 -0800, MitchAlsup@aol.com wrote:
| Quote: | Why not just put some kind of buffer between the inbound instructions
from memory and the consuming side of the decoder. 2 to 4 entries
should be sufficient. With a big multiplexor between the buffer and the
decoder, byte level or nibble level or bit level or anything in between
is doable. You just have to figgure out how fast you can look at a bit
field and compute the length of that instruction.
|
This isn't a hardware-level sim; it's just an ISA simulator. I'm just
trying to decide whether it's worth supporting architectures that may
not actually exist out there...
Dom |
|
| Back to top |
|
|
Christian Bau
Guest
|
| Posted:
Sat Nov 05, 2005 1:15 am Post subject:
Re: Opcode size < instruction memory word size? |
|
|
In article <efsmm1194ipunre7gjcl72h4iqfhvkub1b@4ax.com>,
Dom Gilligan <dg2036@hotmail.com> wrote:
| Quote: | I'm writing a simulator and am wondering about supporting
architectures where a fixed-length opcode is smaller than the
instruction memory width - for example, a 12-bit opcode, but a 16-bit
memory.
I've got a vague recollection that there's an Analog Devices DSP that
does this. Does anyone know if this is the case, or if there are other
processors that do this? Presumably these processors (if they exist)
have word-addressable instruction memory and can't access the unused
bits for opcode fetches, but does anyone know of a byte-addressable
example, where the opcodes fit into memory with no unused bits?
|
Two examples: Control Data Cyber series, with one 60 bit word containing
2, 3 or 4 instructions of 15 or 30 bit. Maybe the Itanium, with three
instructions in a 128 bit word in some strange format. |
|
| Back to top |
|
|
John Savard
Guest
|
| Posted:
Mon Nov 07, 2005 7:56 am Post subject:
Re: Opcode size < instruction memory word size? |
|
|
On Fri, 04 Nov 2005 14:46:36 +0000, Dom Gilligan <dg2036@hotmail.com>
wrote, in part:
| Quote: | I'm writing a simulator and am wondering about supporting
architectures where a fixed-length opcode is smaller than the
instruction memory width - for example, a 12-bit opcode, but a 16-bit
memory.
I've got a vague recollection that there's an Analog Devices DSP that
does this. Does anyone know if this is the case, or if there are other
processors that do this? Presumably these processors (if they exist)
have word-addressable instruction memory and can't access the unused
bits for opcode fetches, but does anyone know of a byte-addressable
example, where the opcodes fit into memory with no unused bits?
|
There was one microprocessor that had 10 bit opcodes, and could have
data memory connected either 8 bits wide or 16 bits wide. I believe it
was the 2650. This sounds like what you're thinking of.
John Savard
http://home.ecn.ab.ca/~jsavard/index.html
http://www.quadibloc.com/index.html
_________________________________________
Usenet Zone Free Binaries Usenet Server
More than 140,000 groups
Unlimited download
http://www.usenetzone.com to open account |
|
| Back to top |
|
|
Joe Pfeiffer
Guest
|
| Posted:
Mon Nov 07, 2005 9:15 am Post subject:
Re: Opcode size < instruction memory word size? |
|
|
Dom Gilligan <dg2036@hotmail.com> writes:
| Quote: | I'm writing a simulator and am wondering about supporting
architectures where a fixed-length opcode is smaller than the
instruction memory width - for example, a 12-bit opcode, but a 16-bit
memory.
|
I'm completely missing why the opcode width would have any
relationship to the instruction memory size, at all.
First, I'm not sure what you mean by instruction memory size. To me,
this would be the size of the instruction memory in a Harvard
architecture machine... and there is no possible way the width of the
opcode could be related to this memory size.
Trying to take a guess what else you might mean, I'm able to imagine
some sort of weird microcode implementation in which the opcode is
simply an address in the microcode of where the code to implement the
opcode starts... which certainly makes no more sense than the first
idea, and maybe less.
So what do you mean? I feel like you must be using either opcode
width or instruction memory size in a way I don't remember seeing
before.
--
Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605
Department of Computer Science FAX -- (505) 646-1002
New Mexico State University http://www.cs.nmsu.edu/~pfeiffer
skype: jjpfeifferjr |
|
| Back to top |
|
|
George Neuner
Guest
|
| Posted:
Mon Nov 07, 2005 9:15 am Post subject:
Re: Opcode size < instruction memory word size? |
|
|
On 06 Nov 2005 20:24:05 -0700, Joe Pfeiffer <pfeiffer@cs.nmsu.edu>
wrote:
| Quote: | Dom Gilligan <dg2036@hotmail.com> writes:
I'm writing a simulator and am wondering about supporting
architectures where a fixed-length opcode is smaller than the
instruction memory width - for example, a 12-bit opcode, but a 16-bit
memory.
I'm completely missing why the opcode width would have any
relationship to the instruction memory size, at all.
:
So what do you mean? I feel like you must be using either opcode
width or instruction memory size in a way I don't remember seeing
before.
|
The OP is referring to one or both of the following:
- architectures which allow constant data to be encoded in the
instruction, ie. a 12-bit opcode plus a 4-bit constant packed in a
16-bit word.
- VLIW architectures in which one word of memory contains more than
one instruction.
To the OP:
The Analog Devices 2106x SHARC series of DSPs is about as strange as
you can find. The SHARC supports 16 mega-words of 48-bit instructions
each containing up to three 16-bit opcodes which are executed in
parallel; 4 giga-words of data memory which can be 16/32-bit integer
or 16/32/40-bit floating point; and 16/32-bit DMA.
George
--
for email reply remove "/" from address |
|
| Back to top |
|
|
Michael Koenig
Guest
|
| Posted:
Tue Nov 08, 2005 1:15 am Post subject:
Re: Opcode size < instruction memory word size? |
|
|
George Neuner wrote:
| Quote: | The OP is referring to one or both of the following:
- architectures which allow constant data to be encoded in the
instruction, ie. a 12-bit opcode plus a 4-bit constant packed in a
16-bit word.
|
Well, that would be practically every RISC architecture and then some...
I have to admit that I thought he meant something like PIC16, where
instructions have a width of 14 bit but data is addressed as 8 bit. But like
someone else mentioned, in that case it doesn't matter much due to the Harvard
architecture storing code and data in separate memories.
--
M.I.K.e |
|
| Back to top |
|
|
Alex Colvin
Guest
|
| Posted:
Tue Nov 08, 2005 9:01 pm Post subject:
Re: Opcode size < instruction memory word size? |
|
|
| Quote: | I've been away for a couple of days; sorry about the confusion. I was
looking for cases where the opcode word size was less than the word
size of whatever memory it was fetched from, meaning that some bits of
the "instruction memory" were unused. For a Von Neumann architecture,
these bits might be used for something else, but that wasn't my
concern.
|
I believe some old Harvard-architecture machines included parity with
instructions fetched from instruction memory. Instruction parity may also
have been a feature in microprogram memories.
There have been CPUs with unused instruction bits. The GE 635 didn't use
bits 27 and 29 of a 36-bit-word instruction. Bit 27 was a general-purpose
interrupt disable.
Plenty of CPUs have undefined opcodes or operands for some instructions.
Opportunities for steganography...
--
mac the naïf |
|
| Back to top |
|
|
George Neuner
Guest
|
| Posted:
Tue Nov 08, 2005 11:23 pm Post subject:
Re: Opcode size < instruction memory word size? |
|
|
On 7 Nov 2005 20:30:12 GMT, Michael Koenig <mikenospam@email.deMUNGED>
wrote:
| Quote: | George Neuner wrote:
The OP is referring to one or both of the following:
- architectures which allow constant data to be encoded in the
instruction, ie. a 12-bit opcode plus a 4-bit constant packed in a
16-bit word.
Well, that would be practically every RISC architecture and then some...
|
The OP said
"a fixed-length opcode is smaller than the instruction memory width"
I interpreted that to mean word size, but I suppose it could also mean
a wide memory bus design that can fetch more than one instruction with
a single read. There's a fair number of those around too.
George
--
for email reply remove "/" from address |
|
| Back to top |
|
|
Dom Gilligan
Guest
|
| Posted:
Wed Nov 09, 2005 1:15 am Post subject:
Re: Opcode size < instruction memory word size? |
|
|
I've been away for a couple of days; sorry about the confusion. I was
looking for cases where the opcode word size was less than the word
size of whatever memory it was fetched from, meaning that some bits of
the "instruction memory" were unused. For a Von Neumann architecture,
these bits might be used for something else, but that wasn't my
concern.
Anyway, the CDC, Itanium, and 2650 examples look good, so I think I'll
get around to supporting this at some stage.
Cheers -
Dom |
|
| Back to top |
|
|
Terje Mathisen
Guest
|
| Posted:
Wed Nov 09, 2005 9:15 am Post subject:
Re: Opcode size < instruction memory word size? |
|
|
Alex Colvin wrote:
| Quote: | Plenty of CPUs have undefined opcodes or operands for some instructions.
Opportunities for steganography...
|
This is in fact extremely common, in the form of encrypted viruses which
employ a decryption algorithm which is polymorphically encoded so as to
make life harder for virus signature detectors.
I clearly remember the first time I disassembled such a virus, probably
the first ever instance: The author/cracker/louse had used multiple
alternative groups of registers, along with a varying number of 'noise'
opcodes that didn't actually affect the algorithm.
The only generic way to detect such a beast is to observe what it is
doing, something which is complicated by the fact that they usually
employ a lot of anti-debugging measures.
I.e. in the example above I had to manually replace the stack pointer
with another register to allow single-stepping.
Terje
--
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching" |
|
| Back to top |
|
|
|
|
|
|
FAQ
Memberlist
Register
Profile
Log in to check your private messages
Log in