| Author |
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Joerg
Guest
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 Posted:
Thu Dec 01, 2005 1:15 am Post subject:
Ever 'souped up' the ADC on Renesas uC? |
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Hello All,
Can anyone share their experience on pushing the envelope of the 10bit
ADC on Renesas micro controllers?
The specs say it's +/-3LSB for non-linearity in 10bit mode but I wonder
how far this and the effective number of bits can be pushed if doing a
stagger/average scheme on signals in the audio range. IOW where you
don't need the full speed. One concern is that they require Vref to be
equal to VCC (I wonder what they were thinking...).
If you needed support how good was it? Any chip availability problems
down the line? I have read mixed opinions especially by lower volume
users but some of that was from a long time ago.
Regards, Joerg
http://www.analogconsultants.com |
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Noway2
Guest
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| Posted:
Thu Dec 01, 2005 5:15 pm Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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My experience with the ADC on the Renesas microcontrollers is that it
is "So-So". I am presently working on a redesign of the project that
used the Renesas processor with something else, largely because of the
ADC accuracy. I found that I was not able to get enough channel -
channel or device - device consistency for the product. The
application requires metering of phase voltages and currents for power
quality and motor control.
As far as technical support goes, I personally think they are one of
the worst companies I have had to deal with, but then the product
volume is somewhat low. |
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joep
Guest
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| Posted:
Fri Dec 02, 2005 12:18 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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I am just curious, your thinking about routing the same analog signal
to multiple A/D inputs, averaging the signals, and hoping the different
non-linear errors on different A/D inputs will be reduced via an RSS
error analysis?
I would think the non-linear errors within a single mux A/D would be
highly correlated and not at all independent? Again, just curious,
don't know any answers to your questions. |
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Jim Stewart
Guest
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| Posted:
Fri Dec 02, 2005 12:36 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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joep wrote:
| Quote: | I am just curious, your thinking about routing the same analog signal
to multiple A/D inputs, averaging the signals, and hoping the different
non-linear errors on different A/D inputs will be reduced via an RSS
error analysis?
I would think the non-linear errors within a single mux A/D would be
highly correlated and not at all independent? Again, just curious,
don't know any answers to your questions.
|
The only thing that I would add is that I've
been disappointed every time but once that I've
tried to push a chip past it's published specs. |
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Joerg
Guest
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| Posted:
Fri Dec 02, 2005 1:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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Hello Meindert,
| Quote: | Of course, that often requires not to heed advice such as separating
AGND and DGND (such separation has never worked for me).
Can you tell me some more about that last statement?
I'm currently laying out a board with a dual 500Msps DDS and am trying to
make the best of the AVDD/DVDD and AGND/DGND separation. But when I think
about it, I can always find a reason why this separation is not such a good
idea. And since I'm doing a multilayer board with VDD/GND planes, the
question raises again if this separation is really necessary.
|
In about 20 years on the roll I have yet to find a situation where
splitting ground planes works. Except, of course, when regulatory or
safety issues mandate it such as is the case in patient interfaces.
Think about it: The analog path goes to some other places. So does the
digital path. Now you could run all signals differentially, buy out a
ferrite manufacturer and place several pounds of common mode chokes
everywhere. But chances are you end up with huge loops anyway and the
brunt of the resulting unwanted signals will be burdened upon the poor
DDS chips because that's where the grounds split. That can lead to
unexplained noises and some egg in the face at the EMC test site.
The most striking effect I saw was with an ADC board that had to run
four ganged 25MSPS 12bit converters and the utmost phase tracking was
required. The designer had split the plane in one long stretch right
under those ADCs. I suggested not doing that but folks were skeptical
since the data sheet recommended it. Then one night I soldered it all
shut on one board using up almost a quarter roll of solder, plopped the
board into the system, noise problems gone.
The best bet in my eyes is to be very diligent about bypassing, use the
correct trace impedance (trace width) and terminate accordingly. I use
mostly AC termination.
Regards, Joerg
http://www.analogconsultants.com |
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Meindert Sprang
Guest
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| Posted:
Fri Dec 02, 2005 1:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message
news:j4Jjf.22785$D13.5086@newssvr11.news.prodigy.com...
| Quote: | Of course, that often requires not to heed advice such as separating
AGND and DGND (such separation has never worked for me).
|
Hi Joerg,
Can you tell me some more about that last statement?
I'm currently laying out a board with a dual 500Msps DDS and am trying to
make the best of the AVDD/DVDD and AGND/DGND separation. But when I think
about it, I can always find a reason why this separation is not such a good
idea. And since I'm doing a multilayer board with VDD/GND planes, the
question raises again if this separation is really necessary.
Meindert |
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Joerg
Guest
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| Posted:
Fri Dec 02, 2005 1:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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Hello Jim,
| Quote: | Not quite. What I wanted to do is an old trick. S/H -> convert, then
inject 1/4LSB offset, S/H -> convert -> add, inject 1/2LSB offset, and
so on. However, this scheme won't help much in cases where the innards
of the converter aren't good enough.
Do you REALLY need to do this ? - what about a better class of ADC,
like seen on the new Analog Devices ARMs - ADuC7019 et al ?
These also have 12 bit, 1Msps, with typical spec of 0.5 LSB DNL,
so there is room to further average...
[ They also have 12 bit DACs ]
|
I need to. The reason is the usual: $$ and power consumption. The only
alternative would be an MSP430 but the versions with HW multiplier and
14bit ADC are too expensive and the specs on that ADC are, well, skimpy.
Got to stay around 2 1/2 bucks for the uC in qties.
| Quote: | If you really must push the ADC, then consider a larger sweep ? : It is
better to sweep the injected offset over, say 16 LSB steps, and average
the results as you then smooth the step variances seen in SAR ADCs.
If you just go 1/4; 1/2; 3/4 you are too locked to a single error point.
|
Yes, I just gave an example. I'll do a much larger sweep since this ADC
can be clocked at 10MHz and requires around 60 cycles to complete a
10bit conversion. I only need a few kHz of effective sample rate.
| Quote: |
This trades off speed for more precision, and you are using the ADC as
a precision comparitor, and adding a Slope ADC underneath the std SAR one.
I've heard various horror stories about some of the 'generic ADCs'
that come with uC. Many don't even fill out the MAX column, and only
spec typicals...
|
That's exactly why I posted. The specs on the Renesas are a wee bit more
detailed than on the TI MSP series. But they still leave a lot to be
desired and every time I had asked any uC vendor for more info on more
analog details all I got was a blank stare.
Regards, Joerg
http://www.analogconsultants.com |
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Joerg
Guest
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| Posted:
Fri Dec 02, 2005 1:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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Hello Steve,
Well, yes. But it is easier to inject offsets. Adding four bits of
offset (in theory) takes just four resistors and four port pins.
Regards, Joerg
http://www.analogconsultants.com |
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Jim Granville
Guest
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| Posted:
Fri Dec 02, 2005 1:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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Joerg wrote:
| Quote: | Hello Joep (or Steve?),
I am just curious, your thinking about routing the same analog signal
to multiple A/D inputs, averaging the signals, and hoping the different
non-linear errors on different A/D inputs will be reduced via an RSS
error analysis?
Not quite. What I wanted to do is an old trick. S/H -> convert, then
inject 1/4LSB offset, S/H -> convert -> add, inject 1/2LSB offset, and
so on. However, this scheme won't help much in cases where the innards
of the converter aren't good enough.
|
Do you REALLY need to do this ? - what about a better class of ADC,
like seen on the new Analog Devices ARMs - ADuC7019 et al ?
These also have 12 bit, 1Msps, with typical spec of 0.5 LSB DNL,
so there is room to further average...
[ They also have 12 bit DACs ]
If you really must push the ADC, then consider a larger sweep ? : It is
better to sweep the injected offset over, say 16 LSB steps, and average
the results as you then smooth the step variances seen in SAR ADCs.
If you just go 1/4; 1/2; 3/4 you are too locked to a single error point.
This trades off speed for more precision, and you are using the ADC as
a precision comparitor, and adding a Slope ADC underneath the std SAR one.
I've heard various horror stories about some of the 'generic ADCs'
that come with uC. Many don't even fill out the MAX column, and only
spec typicals...
-jg |
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Joerg
Guest
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| Posted:
Fri Dec 02, 2005 1:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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Hello Joep (or Steve?),
| Quote: | I am just curious, your thinking about routing the same analog signal
to multiple A/D inputs, averaging the signals, and hoping the different
non-linear errors on different A/D inputs will be reduced via an RSS
error analysis?
|
Not quite. What I wanted to do is an old trick. S/H -> convert, then
inject 1/4LSB offset, S/H -> convert -> add, inject 1/2LSB offset, and
so on. However, this scheme won't help much in cases where the innards
of the converter aren't good enough.
Regards, Joerg
http://www.analogconsultants.com |
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Joerg
Guest
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| Posted:
Fri Dec 02, 2005 1:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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Hello Jim,
| Quote: |
The only thing that I would add is that I've
been disappointed every time but once that I've
tried to push a chip past it's published specs.
I can't say that. When there was no other option I have pushed |
especially ADC systems way past that point. Things like ganging,
controlled offset and phase shifts with feedback and so on. There were
times when even seasoned FAEs said "you can't do this" but we did it.
Sometimes it was the only way to detect really tiny Doppler shifts.
Of course, that often requires not to heed advice such as separating
AGND and DGND (such separation has never worked for me).
Regards, Joerg
http://www.analogconsultants.com |
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Steve at fivetrees
Guest
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| Posted:
Fri Dec 02, 2005 1:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message
news:e0Jjf.22784$D13.2400@newssvr11.news.prodigy.com...
| Quote: |
Not quite. What I wanted to do is an old trick. S/H -> convert, then
inject 1/4LSB offset, S/H -> convert -> add, inject 1/2LSB offset, and so
on. However, this scheme won't help much in cases where the innards of the
converter aren't good enough.
|
Similarly one can inject noise and oversample:
http://en.wikipedia.org/wiki/Oversampling
But you knew that ;).
Steve
http://www.fivetrees.com |
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Meindert Sprang
Guest
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| Posted:
Fri Dec 02, 2005 9:15 am Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message
news:KbLjf.21521$BZ5.3550@newssvr13.news.prodigy.com...
<...>
| Quote: | The best bet in my eyes is to be very diligent about bypassing, use the
correct trace impedance (trace width) and terminate accordingly. I use
mostly AC termination.
|
Thanks for that story Joerg. It sort of confirms what I already thought. The
idea of having all that 'error'-current flow though your chip and bonding
has always seemed odd to me.
Regards,
Meindert |
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joep
Guest
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| Posted:
Fri Dec 02, 2005 5:15 pm Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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"Likewise, the ground connections
(AGND, DGND) should be kept separate as far back to the
source as possible (i.e., separate the ground planes on a localized
board, even if the grounds connect to a common point in
the system)."
Hmm, thats interesting, Ok, I guess I see your confusion, my comment
was from my experence with the datasheets I have read, which is only a
small percentage of the available parts, so I spoke to hastily.
Relooking at some of Bryant's lecture notes (the author of the
reference article) I noticed he did comment on data sheet writers FWIW
Bryant quote
"Most ADCs have separate analog ground (AGnd) and digital ground (DGnd)
pins, but too many engineers, and, unfortunately, too many data sheet
writers as well, are uncertain how they should be connected. The
lecture considers the nature of the currents flowing in these pins, the
vulnerabilities of precision data converters to internal and external
noise, and the effects of various grounding and decoupling
configurations, and suggests, and justifies, a grounding scheme which
gives the best possible converter performance in the vast majority of
cases."
that lecture is here
http://www.techonline.com/community/tech_group/analog/course/13479
In any case I wouldn't second guess the datasheet writer, I would ask
Analog Devices for clarification on this point for this particular
part, there are always exceptions to the rule, and errors in the
datasheet, you have to found out which it is. |
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joep
Guest
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| Posted:
Fri Dec 02, 2005 5:15 pm Post subject:
Re: Ever 'souped up' the ADC on Renesas uC? |
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In general I don't think mixed signal device manufacturers recommend
separation of AGND and DGND, so I'm not sure where everyone is getting
this advice from
This is the best collection of articles I have seen concerning the
problem of mix signal devices and grounding, from the horses mouth
(analog devices)
http://www.analog.com/UploadedFiles/Associated_Docs/217348021sect7b.pdf
For mixed signal devices you should connect the digital and analog
ground to the analog ground with the shortest leads as possible. Its a
compromise but the best compromise possible with a mixed signal device
(and the reason why mixed signal devices are inherently inferior to
separate pure analog and digital devices, all other things being
equal). Refer to the referenced document for good info and explanations
of what's really happening and the logic behind it. (see page 3). |
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