| Author |
Message |
MaheshS
Guest
|
 Posted:
Tue Dec 06, 2005 5:15 pm Post subject:
Flash Interface with AT91RM9200 |
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Hi,
I am doing a prototype baord based on AT91RM9200.I am planning to use
Intel Strataflash memory (E28F640J3A)on the board.This flash memory i
having a program enable input.How can i connect this to the processor
while interfacing?If anyone is using the same flash, please suggest.
Also I would like to understand how does the USB_DP_PUP signa
enable/disable the pull-up resistor on DP?(Ref: Interfacing USB Devic
peripheral-AT91RM9200 datasheet)
Best regards,
S Mahesh. |
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PeteS
Guest
|
| Posted:
Tue Dec 06, 2005 5:15 pm Post subject:
Re: Flash Interface with AT91RM9200 |
|
|
MaheshS wrote:
| Quote: | Hi,
I am doing a prototype baord based on AT91RM9200.I am planning to use
Intel Strataflash memory (E28F640J3A)on the board.This flash memory is
having a program enable input.How can i connect this to the processor,
while interfacing?If anyone is using the same flash, please suggest.
|
The VPEN pin is used to lock/unlock the device globally for writing. If
you wish to have some certainty that the device may not be written to
in a spurious manner (during startup/shutdown, for example), connect
this pin (with a pulldown of about 100k) to an IO port bit. The
pulldown will ensure VPEN is invalid until the processor starts up and
initialises the port bit, preventing spurious writes. If you believe
there should be no problem, pull the line to Vdd through 100k. This
will make the device unlocked (at that level, anyway) at all times.
Note you still have to write to the device to unlock blocks.
| Quote: | Also I would like to understand how does the USB_DP_PUP signal
enable/disable the pull-up resistor on DP?(Ref: Interfacing USB Device
peripheral-AT91RM9200 datasheet)
|
The USB spec can clear this up. An upstream (slave) port has to signal
it is present. It does this by pulling the DP line high through 1.5k,
1%. Releasing this line permits the downstream (host) to pull *both*
lines low (through 15k). With both lines low, no active device is
assumed to be attached.
| Quote: | Best regards,
S Mahesh.
|
Cheers
PeteS |
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MaheshS
Guest
|
| Posted:
Thu Dec 08, 2005 4:32 pm Post subject:
Re: Flash Interface with AT91RM9200 |
|
|
| Quote: | MaheshS wrote:
Hi,
I am doing a prototype baord based on AT91RM9200.I am planning t
use
Intel Strataflash memory (E28F640J3A)on the board.This flash memory is
having a program enable input.How can i connect this to the processor,
while interfacing?If anyone is using the same flash, please suggest.
The VPEN pin is used to lock/unlock the device globally for writing. If
you wish to have some certainty that the device may not be written to
in a spurious manner (during startup/shutdown, for example), connect
this pin (with a pulldown of about 100k) to an IO port bit. The
pulldown will ensure VPEN is invalid until the processor starts up and
initialises the port bit, preventing spurious writes. If you believe
there should be no problem, pull the line to Vdd through 100k. This
will make the device unlocked (at that level, anyway) at all times.
Note you still have to write to the device to unlock blocks.
Also I would like to understand how does the USB_DP_PUP signal
enable/disable the pull-up resistor on DP?(Ref: Interfacing USB Device
peripheral-AT91RM9200 datasheet)
The USB spec can clear this up. An upstream (slave) port has to signal
it is present. It does this by pulling the DP line high through 1.5k,
1%. Releasing this line permits the downstream (host) to pull *both*
lines low (through 15k). With both lines low, no active device is
assumed to be attached.
Best regards,
S Mahesh.
Cheers
PeteS
Hi |
Thanks for the suggestion. If we are using a single flash memory IC, i
it possible to have a glueless connection? in that case, can we connec
the chip select signal from controller directly to CE0 (with CE1 and CE
connected to GND)?
Regards,
S Mahesh. |
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