| Author |
Message |
Abbs
Guest
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 Posted:
Wed Dec 07, 2005 4:12 pm Post subject:
VERIFICATION AND TESTING |
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Hi.
This group is of real help to people that really need help and
assistance during the course of designing and programning. Well, all
these while i was into desiging and development. now i have been
shifted to VERIFICATION and TESTING in VHDL. i have done verification
earlier in TESTBENCHES, wrote a code and given input vectors and
verified the output vectors. Is this basically how testing is done, or
lots more into it. I'am just aware of this way of testing of the VHDL
code in TESTBENCHES.
If there are many other ways of testing and validation which i'am
unaware of PLEASE let me know.
I'am refering a book:
Writing Testbenches: Functional Verification of HDL Models, Second
Edition
by Janick Bergeron.
well its just the begening.
Can i please be informed of sites or pdf doc that will help me gain
more knowledge in this.
Along with this i request to get info, ideas on the importance,
advantages, of testing, diffrent tools used in verification.
One last doubt, in verification, do we even work on STATIC TIME
ANALYSIS and SYNTHESIS.
or this is done by the designer itself..
would be very thankful to get replies soon.
Cheers
Bye |
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Thomas Stanka
Guest
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| Posted:
Thu Dec 08, 2005 9:15 am Post subject:
Re: VERIFICATION AND TESTING |
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| Quote: | code in TESTBENCHES.
If there are many other ways of testing and validation which i'am
unaware of PLEASE let me know.
|
Code review, testbenches, static timing analyses and formal
verification are the major verification tasks. Don't know which of them
makes sense for your designs and team.
| Quote: | One last doubt, in verification, do we even work on STATIC TIME
ANALYSIS and SYNTHESIS. or this is done by the designer itself..
|
How could we know if you don't? STA is usually perfomed after layout,
has your designer feedback from layout? Do you have to verify after
layout or are you only responsible for functional verification until
synthesis?
bye Thomas |
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Abbs
Guest
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| Posted:
Thu Dec 08, 2005 4:48 pm Post subject:
Re: VERIFICATION AND TESTING |
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Thomas Stanka wrote:
| Quote: | code in TESTBENCHES.
If there are many other ways of testing and validation which i'am
unaware of PLEASE let me know.
Code review, testbenches, static timing analyses and formal
verification are the major verification tasks. Don't know which of them
makes sense for your designs and team.
One last doubt, in verification, do we even work on STATIC TIME
ANALYSIS and SYNTHESIS. or this is done by the designer itself..
How could we know if you don't? STA is usually perfomed after layout,
has your designer feedback from layout? Do you have to verify after
layout or are you only responsible for functional verification until
synthesis?
bye Thomas
|
hi
i was told to study corner case testing, different testing scenarios
and BFM models. i have to test the design before the layout. before
after synthesis not to sure... i wana get good knowledge regarding
verification. can you help me with links that gives a brief idea
related to testing...
thanks
Bye |
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Hans
Guest
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| Posted:
Sat Dec 10, 2005 1:16 am Post subject:
Re: VERIFICATION AND TESTING |
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Hi Abbs,
Do a search on the web for Transaction Level Modelling (TLM), Constraint
Random (CR) stimulus generations, assertions (like PSL/SVA/OVL) and
functional and formal verification.
Hans
www.ht-lab.com
"Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message
news:1134038928.859327.248170@o13g2000cwo.googlegroups.com...
| Quote: |
Thomas Stanka wrote:
code in TESTBENCHES.
If there are many other ways of testing and validation which i'am
unaware of PLEASE let me know.
Code review, testbenches, static timing analyses and formal
verification are the major verification tasks. Don't know which of them
makes sense for your designs and team.
One last doubt, in verification, do we even work on STATIC TIME
ANALYSIS and SYNTHESIS. or this is done by the designer itself..
How could we know if you don't? STA is usually perfomed after layout,
has your designer feedback from layout? Do you have to verify after
layout or are you only responsible for functional verification until
synthesis?
bye Thomas
hi
i was told to study corner case testing, different testing scenarios
and BFM models. i have to test the design before the layout. before
after synthesis not to sure... i wana get good knowledge regarding
verification. can you help me with links that gives a brief idea
related to testing...
thanks
Bye
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Abbs
Guest
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| Posted:
Wed Dec 14, 2005 5:15 pm Post subject:
Re: VERIFICATION AND TESTING |
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hiii
i need immeadite help...
i have to deliver a presentation. suppose i have to verify a D flip
flop, what are the verification stages, how will i proceed with it.
what are the steps to begin till end. its important so can any one out
here just brief it out to me.
thanks a million.
bye |
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