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Computer Freak · Guest

Hey guys! I have a coupl eof questions related to caches access time
:
It is very well known that:
Ta = Tc + (1-H)Tm
where Ta = average accesss time
Tc = cache access time
Tm = memory access time
H = hit ratio

Now my questions are:
How would this equation differ if we take into account the writes as
well as reads using a write through policy??? Let Tb = time to transfer
a block or a line from cache to main memory and W is the fraction of
write refrences.

Now supposing we are following the write-back policy, how would the
original equation be modified?? Let Wb = probability that a line in the
cache has been altered.

Thanks a lot guys!!!!! I really appreciate your help.

Guest

Sounds a lot like a homework problem. But I'll bite on it anyway. Just
assume that I will deliberately through in some random errors.

If the memory write policy is write through as you stated in the
problem description, then the probability of a modified cache line is
0.

So the write access approximates to Tm (this ignores that the write
access time of a memory line is different than the read access time of
a full Cache line). Your original formula is the read access time.

-Jim

Computer Freak wrote:

Computer Freak · Guest

thanks Jim, but your answer does not make any sense! You did not just
through in "SOME" random errors. but you provided the WRONG solution,
but thanks for your time anyways.

Del Cecchi · Guest

"Computer Freak" <nivine.dalleh@gmail.com> wrote in message
news:1134204213.729829.127280@g44g2000cwa.googlegroups.com...

Guest

OK, I see the line where the scenario changed to a write back scheme.
Sorry for the confusion, I flat missed that the first two times I read
the original post.

So I'll take another stab at it. Again, some generalities assumed. Most
significantly being that every write to a modified line will require a
flush (no owned state). This is not always the case, but without any
further definition of the cache prococol, it is the simplest.

Ta = ((1-W)(H*Tc+(1-H)Tm)) + W((1-Wb)Tc+(Wb(Tm+Tc)))

(1-W) is the read percentage
H*Tc is the cache access time times the cache hit rate
(1-H) * Tm is the cache miss times the mem access time
The entire first part of the equation is the average read time
component

W is the write percentage
(1-Wb)* Tc is the percentage of times the cache line is unmodified
times the cache write time
Wb*(Tm+Tc) is the modified cache line percentage times the memory
access time plus the cache write time
The entire second part of the equation is the average write time
component

-Jim

Computer Freak wrote:

Guest

OK Del and Freak, I'll keep playing along. What errors??

The modified cache line probability of 0? That is certainly true if you
have a write through policy established. Or does your memory model
somehow have modified cache lines anyway?

So if it doesn't have any modified cache lines, then all you need to
know is the write access time (generally this is the read/modify/write
time of the memory).

Feel free to add any other unstated conditions to your problem such as
write buffers.

But if you want to make a blanket "you are wrong" statement, you'll
have to provide a little more insight into your rational if you want to
gain any credibility.

-Jim

Guest

OK Del and Freak, I'll keep playing along. What errors??

The modified cache line probability of 0? That is certainly true if you
have a write through policy established. Or does your memory model
somehow have modified cache lines anyway?

So if it doesn't have any modified cache lines, then all you need to
know is the write access time (generally this is the read/modify/write
time of the memory).

Feel free to add any other unstated conditions to your problem such as
write buffers.

But if you want to make a blanket "you are wrong" statement, you'll
have to provide a little more insight into your rational if you want to
gain any credibility.

-Jim

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