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HB · Guest

Hi,

I use a Virtex XCV300
I would like to do : a multi *3 and a div /2 with a clk = 32 MHz.
(I would like to obtain a freq = 48 MHz)

Can you help me !!.
Thanks and regards,

Benoit.

Symon · Guest

Benoit,
You could double your 32MHz with a DLL to get 64MHz. Then use a clock enable
to select just 3 out of four clocks. You don't mind a little jitter do you?
Better still, (and I write this in the style of Mr. Alfke ;-)) the Virtex
part to a museum sell, and a modern FPGA with a DCM get.
Cheers, Syms.

"HB" <bhb22l@yahoo.fr> wrote in message
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Austin Lesea · Guest

So it is....

Looks like getting 48 MHz from 32 MHz is not going to be as easy as it
first appears!

What kind of output duty cycle and max jitter is needed?

Austin

Symon wrote:

Symon · Guest

"Austin Lesea" <austin@xilinx.com> wrote in message
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Austin Lesea · Guest

HB,

In Virtex, the DLL may be used for mutliply by 2. That gets you to 64
MHz. Then a subsequent DLL may be used for divide by 1.5 to get 48 MHz.

Or, you may use a /1.5 circuit made out of FF's and a LUT.

http://www.xilinx.com/xcell/xl33/xl33_30.pdf

Austin

HB wrote:

Gabor · Guest

I would suggest using a small external clock multiplier like the
8-pin SOIC ICS501 to multiply the 32 MHz by three. There is
no PLL in the Virtex or Virtex E series.

Symon wrote:

HB · Guest

I need a choice between 2 solutions :

first solution:
I can use a Freq=48MHz to create a 32MHz (multi *2, and div 3).
But the signal for this freq isn't locate at a clock PIN (old card, so I
can't change the PINOUT).
This signal is locate PIN number AA4 in a Virtex XCV300-FG456).
I have some problems to use DLL and BUF.
Is someone could help me (use DLL and/or BUF without dedicated clk pin) !!.

second solution:
I can use a Freq=32MHz to create a 48MHz (multi*3, and div 2).
But it very difficult to have this multi *3 !.

I need a clk with a good precision, and if possible with around 50/50 of
duty cycle.

THANKS LOT for your help. Any suggestion will appreciate.
Regards.

Benoit.

"Austin Lesea" <austin@xilinx.com> a écrit dans le message news:
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Symon · Guest

"HB" <bhb22l@yahoo.fr> wrote in message
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Ray Andraka · Guest

HB wrote:

Gee, that sounds a lot like the GV associates board I used for the Radar
project shown in the gallery page of my website (the one with the CPU
fans on the FPGAs). In that case, there was a 48MHz clock for a USB
interface chip that was also connected to the FPGA, but not through a
clock pin and we had a separate clock oscillator that came through
another pin (I think it was 66 MHz).

If you aren't worried about the relative phase of the 32 and 48 Mhz
clocks, you can bring the 48 Mhz clock in through the non-clock pin and
use general routing resources to get it to a DLL. From there you can do
the divide by 1.5 to get 32 MHz.

I'd have to do some digging through the archives to find the clock
module for that design, but the point is you don't necessarily have to
bring the clock in on a clock pin if you aren't worried about clock skew.

HB · Guest

Hi Ray,

Thanks for your answer. I take an interest in your example. Can you send me
the file.vhd
with the clk rom your project.
My problem is :
I use with success the DLL in my project, but only for a free place and
route.
When I try to write a file.ucf with this dedicated pin "aa4" for my CLK, ISE
(Version7.1)
stop with error at the mapping.
(need to use IBUF or other...)

I aren't worried about the relative phase of the 32 and 48 Mhz clocks, but I
would like to have
duty cycle around 50% (40/60 max).

Thanks for your help.

Benoit.

"Ray Andraka" <ray@andraka.com> a écrit dans le message news:
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Symon · Guest

Benoit,
You need to learn how to search Google groups! ;-)
Look here for example code:-
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/b2e060b33fd0a0a2/c1a2d891c6d6ca77
HTH, Syms

Ray Andraka · Guest

I don't have the vhdl handy at the moment. You need to change your
input buffer from an IBUFG to an IBUF to be able to place it on an
arbitrary pin. You probably don't need to place anything else, nor do
anything else special.