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Message |
avishay
Guest
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Posted:
Wed Dec 14, 2005 1:15 am Post subject:
Frequency dependent SOPC builder components |
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Hello all,
I'm designing a component for integration in Altera's SOPC builder, for
which I have to set some frequency dependent constants (for timing
generation). How can I pass the component's assigned frequency from the
SOPC builder to the VHDL? I can do either with VHDL generic or some
kind of dynamic source code modification using the build script.
Thanks,
Avishay |
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Mark McDougall
Guest
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Posted:
Wed Dec 14, 2005 1:15 am Post subject:
Re: Frequency dependent SOPC builder components |
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avishay wrote:
| Quote: | I'm designing a component for integration in Altera's SOPC builder, for
which I have to set some frequency dependent constants (for timing
generation). How can I pass the component's assigned frequency from the
SOPC builder to the VHDL? I can do either with VHDL generic or some
kind of dynamic source code modification using the build script.
|
If you define a generic in the top level of your component, SOPC should
allow the user to edit the value when they create an instance of the
component.
Regards,
Mark |
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avishay
Guest
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Posted:
Wed Dec 14, 2005 9:15 am Post subject:
Re: Frequency dependent SOPC builder components |
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This wasn't my meaning. In the main SOPC builder screen, a clock is
assigned to each component, and the frequency of each clock is entered
at a separate table. I need access to this information.
Thanks,
Avishay |
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Mark McDougall
Guest
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Posted:
Thu Dec 15, 2005 1:15 am Post subject:
Re: Frequency dependent SOPC builder components |
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avishay wrote:
| Quote: | This wasn't my meaning. In the main SOPC builder screen, a clock is
assigned to each component, and the frequency of each clock is entered
at a separate table. I need access to this information.
|
A quick look in <C:\altera\kits\nios2_51\bin\gtf> shows a file called
MODULE_FREQ.gtf which apparently 'returns the frequency of the indicated
PTF module'. My guess is you need to somehow call this in a customised
build script, and quite possibly generate a VHDL source file from this
information?!?
Regards,
Mark |
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