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fpgabuilder
Guest
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Posted:
Thu Dec 15, 2005 1:15 am Post subject:
consensus theorem and power |
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I am wondering if it is possible to reduce switching activity in the
next state logic if I use consensus theorem (term).
Any thoughts group? I am interested in this discussion from an
academic standpoint and not in the fact that most of the tools will
optimize away the consensus term in a synchronous design.
Thanks.
-sanjay |
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JustJohn
Guest
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Posted:
Thu Dec 15, 2005 8:50 am Post subject:
Re: consensus theorem and power |
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| Quote: | sanjay wrote:
I am wondering if it is possible to reduce switching activity in the
next state logic if I use consensus theorem (term).
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I don't know what you mean by "consensus term", could you elaborate?
If you are talking about overlapping logic terms, these don't make much
difference for LUT logic, which is guaranteed glitchless for single
input transitions.
John |
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fpgabuilder
Guest
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Posted:
Thu Dec 22, 2005 1:16 am Post subject:
Re: consensus theorem and power |
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Hi John,
Sorry for the delay in responding. I am not sure about what you mean
by overlapping logic terms. By consensus term I mean use of the
expression -
ab + a'c = ab + a'c + bc. In this case, bc is the consensus term.
As you probably know, bc prevents any glitches in the output when a
changes. So what I am implying is that the switching activity on the
output is reduced if we use the bc term.
Thanks.
-sanjay |
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Peter Alfke
Guest
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Posted:
Thu Dec 22, 2005 1:16 am Post subject:
Re: consensus theorem and power |
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Sanjay, if you are talking about Look-Up-Table logic, there is no
difference between the approaches.
In your case of three inputs, abc, you must define the output for all 8
possible input codes in the Table (or call it a ROM).
Whether you think of "consensus" has no relevance. LUT logic is a
brute-force implementation.
You get no glitch on the output when you change one input, (well, you
may get a change, but no glitch !) and you also get no glitch when you
change two inputs, provided all 4 permutations of these two iputs
create the same output (not true in your specific example).
Peter Alfke, Xilinx Applications |
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