Guest
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 Posted:
Sun Dec 18, 2005 9:01 am Post subject:
How to use ISE FPGA Editor to compare timing path easily? |
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Hi,
I have a memory controller desing implemented for Virtex4 chip. I
know there are some timing problem and suspect that it is because the
delay difference between the different timing pathes are too much.
There is a common clock generated from DCM driving all the logic.
Currently I launtch the desing in FPGA Editor and try to collect the
delay for all the pathes, but that is really a lot of work. I start
from the DCM output, count the delay one net by one net up to the pad,
and sum them up.
And do this for all the pathes seem impossible.
I wonder if there are any trick to do this kind of thing faster?
Thanks. |
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Duane Clark
Guest
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| Posted:
Sun Dec 18, 2005 5:15 pm Post subject:
Re: How to use ISE FPGA Editor to compare timing path easily |
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linq936@hotmail.com wrote:
| Quote: | Hi,
I have a memory controller desing implemented for Virtex4 chip. I
know there are some timing problem and suspect that it is because the
delay difference between the different timing pathes are too much.
There is a common clock generated from DCM driving all the logic.
Currently I launtch the desing in FPGA Editor and try to collect the
delay for all the pathes, but that is really a lot of work. I start
from the DCM output, count the delay one net by one net up to the pad,
and sum them up.
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Are you not using the FFs in the IOBs? If not, why not?
To specifically answer your question, in a case where for some reason
you do not want to use the IOB FFs, the easy way to do that is to set a
timing constraint for FF to PAD delay for the paths in question. Then
the static timing report (*.twr) will tell you exactly what paths are
failing, and exactly what all the delays are within those failing paths. |
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