| Author |
Message |
javi
Guest
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 Posted:
Tue Dec 20, 2005 5:16 pm Post subject:
FPGA implementation complexity |
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Hi everyone,
I have to estimate the complexity of an algorithm, with respect to
future implementation in an FPGA (that is, I have to estimate the require
gates and area). To do that, I should take into account the number o
adders, multipliers,multiplexers, delay lines and so on that are needed t
implement the algorithm, and the required bitwith of the inputs for ever
one of the operations.
However, I am very new at this field, and I have no general rule as to ho
the bitwidth is related to the number of gates for every one of thes
operations. I would be grateful if anybody could recommend me some we
page or book where this type of analysis is done. I am looking for a rul
of thumb to be able to do the estimation, and not for a specifi
implementation of a particular FPGA.
Thanks in advance for your help,
Javi |
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Guest
|
| Posted:
Tue Dec 20, 2005 5:16 pm Post subject:
Re: FPGA implementation complexity |
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javi wrote:
| Quote: | Hi everyone,
I have to estimate the complexity of an algorithm, with respect to a
future implementation in an FPGA (that is, I have to estimate the required
gates and area). To do that, I should take into account the number of
adders, multipliers,multiplexers, delay lines and so on that are needed to
implement the algorithm, and the required bitwith of the inputs for every
one of the operations.
However, I am very new at this field, and I have no general rule as to how
the bitwidth is related to the number of gates for every one of these
operations. I would be grateful if anybody could recommend me some web
page or book where this type of analysis is done. I am looking for a rule
of thumb to be able to do the estimation, and not for a specific
implementation of a particular FPGA.
Thanks in advance for your help,
|
FPGAs are fairly coarse grained things - you don't deal with individual
gates, and gate counts aren't particularly useful. Tell the person who
asked you for a gate count that they are wrong (unless it was your
boss, of course).
A more useful metric would be slice or CLB count. Flip flop and LUT
count would be as fine grained as you should go.
Don't forget about packing density - routing difficultlies may stop you
from being able to use more than about 50% of the flip flops and LUTs
on the chip (unless you're Ray Andraka or someone with similar
experience).
To paraphrase an old comp.arch.fpga post "You pay for the routing; the
logic is free."
Some FPGAs also have dedicated multipliers or DSP blocks. These are
limited in number (never more than a few hundred) and you have the
choice of using them (thus making your design non-portable) or
implementing your algorithm in the more general FPGA fabric, which is
harder and possibly more expensive.
In any case, the only real way to answer you question is to implement
the design in a real FPGA and read the report file from the tools.
This is off-topic for comp.dsp. Ask you question again in
comp.arch.fpga.
Regards,
Allan |
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Bhaskar Thiagarajan
Guest
|
| Posted:
Wed Dec 21, 2005 12:39 am Post subject:
Re: FPGA implementation complexity |
|
|
<allanherriman@hotmail.com> wrote in message
news:1135098339.190112.148360@g44g2000cwa.googlegroups.com...
| Quote: | javi wrote:
Hi everyone,
I have to estimate the complexity of an algorithm, with respect to a
future implementation in an FPGA (that is, I have to estimate the
required
gates and area). To do that, I should take into account the number of
adders, multipliers,multiplexers, delay lines and so on that are needed
to
implement the algorithm, and the required bitwith of the inputs for
every
one of the operations.
However, I am very new at this field, and I have no general rule as to
how
the bitwidth is related to the number of gates for every one of these
operations. I would be grateful if anybody could recommend me some web
page or book where this type of analysis is done. I am looking for a
rule
of thumb to be able to do the estimation, and not for a specific
implementation of a particular FPGA.
Thanks in advance for your help,
FPGAs are fairly coarse grained things - you don't deal with individual
gates, and gate counts aren't particularly useful. Tell the person who
asked you for a gate count that they are wrong (unless it was your
boss, of course).
A more useful metric would be slice or CLB count. Flip flop and LUT
count would be as fine grained as you should go.
Don't forget about packing density - routing difficultlies may stop you
from being able to use more than about 50% of the flip flops and LUTs
on the chip (unless you're Ray Andraka or someone with similar
experience).
To paraphrase an old comp.arch.fpga post "You pay for the routing; the
logic is free."
Some FPGAs also have dedicated multipliers or DSP blocks. These are
limited in number (never more than a few hundred) and you have the
choice of using them (thus making your design non-portable) or
implementing your algorithm in the more general FPGA fabric, which is
harder and possibly more expensive.
In any case, the only real way to answer you question is to implement
the design in a real FPGA and read the report file from the tools.
This is off-topic for comp.dsp. Ask you question again in
comp.arch.fpga.
Regards,
Allan
|
Allan has given you some good advice.
You say that you don't have any experience in implementing DSP algorithms on
FPGAs (I'm not even sure if you've implemented simple logic in FPGAs). Given
this, it seems unreasonable (on your manager's part) to ask you to figure
out this sort of an estimate. It's very similar to asking someone who has no
DSP programming experience to figure out if a certain algorithm will run
real time on a certain DSP (except this is much harder).
The whole topic of DSP on FPGAs is very poorly addressed on the web and in
books - so you'll be hard pressed to find any reference material related to
your task. I did post some references for DSP using FPGAs recently - so do a
google search for my post and see if any of the references addresses this
area.
Cheers
Bhaskar |
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Chris.Gammell
Guest
|
| Posted:
Wed Dec 21, 2005 11:43 pm Post subject:
Re: FPGA implementation complexity |
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Hey Javi,
I'm also in a similar situation as you, as a beginner to DSP working o
FPGA stuff. Although I cannot possibly begin to estimate for you th
complexity of your design, I do have some other things to mention to yo
that may help. First, is to check out the following book. It is startin
to get a little dated in terms of technology, but the concepts ar
accurate:
"Digital Signal Processing with Field Programmable Gate Arrays" U
Meyer-Baese isbn 3-540-41341-3
That book mainly deals with VHDL. Also, I don't know if your company ha
the resources to do so, but if they do, there are high level block diagra
software programs that allow you to design the data flow through you
system in Simulink and then it will translate it to VHDL or Verilog fo
you. One is Xilinx System Generator and another is SynplifyDSP (m
preference due to the better support). I believe they now have on
targeted for Altera parts too, although SynplifyDSP can target most parts
Once again, you need a good deal of cash up front to get these tools, but
think they are very helpful and they are basically how I have learned DS
stuff.
The reason I mention the Simulink tools is that you can also put togethe
a very rough design in that program and it will estimate slice usage fo
you, at which point you can start to determine what kind of part you woul
like to target.
Good luck!
Chris |
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