himassk
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 Posted:
Wed Dec 21, 2005 4:46 pm Post subject:
SD memory protocol timing issue |
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Hi,
In SD memory Physical layer specification Version 1.10 written that:
Reference to Page no 75, Fig 25 Identification Timing:
The timing for CMD2 and ACMD41 is:
The command is followed by a period of two Z bits (allowing time for
direction switching on the bus) and then by P bits pushed up by the
responding card. The card response to
the host command starts after NID clock cycles. (NID = 5 clock cycles)
My question is:
1. The card has to push P bits exactly after two Z bits or can it take
more time ?
2. The card has to respond to the host command exactly after 5 clock
cycle ?
Please clarify me.
Regards,
HimaSSK. |
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