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I. Ulises Hernandez · Guest

Hi guys,

I've written a DDR controller, runs on a virtex2 and interfaces a sodimm
256MB.

I've got a problem initialisating a DDR, it works 10 out of 11 times (random
tbh, but fails once in a blue moon). I am not sure what it could be as I am
doing all that the JEDEC specs during the initialization process... with the
EXCEPTION of holding CKE low during power-up. I can NOT control the value of
that signal during power-up because the FPGA has not been programmed yet
(it's programmed from Flash). And there is not external pull-down.

The JEDEC standard for DDR specs that:

"Except for CKE, inputs are not recognized as valid
until after VREF is applied. CKE is anSSTL_2 input,
but will detect an LVCMOS LOW level after VDD is
applied. Maintaining an LVCMOS LOW level on
CKE during power--up is required to guarantee that
the DQ andDQS outputs will be in the High--Z state,
where they will remain until driven in normal operation
(by a read access). After all power supply and
reference voltages are stable, and the clock is
stable, the DDR SDRAM requires a 200 µs delay
prior to applying an executable command."

They recommend that:

"Operation or timing that is not specified is illegal and after such an
event, in order to guarantee
proper operation, the DRAM must be powered down and then restarted through
the specified
initialization sequence before normal operation can continue."

So... when the FPGA is not programmed the DDR control signals are floating,
they could mimic a DDR access and put the DDR into an odd state, is that
correct? If so, what do they mean by "DRAM must be powered down and then
restarted...", do they mean a CKE high to low transition which in theory
puts the DDR into power down mode...?

Any help would be appreciatted, thanks in advance,

--
Ignacio Ulilses Hernandez
" I'm not normally a praying man, but if you're up there, please save me,
Superman!" - Homer Simpson ;O)

Guest

Hi,
Put a pull-down on CKE pin that would make CKE low when power is up and
DONE pin of FPGA is low.

That will make sure that there are no unstable conditions for the DDR
chip.

Weng

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