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Morten Leikvoll · Guest

Below is the code I use to mux 8 asynchronous clocks on a Spartan3. I guess
this method is safer than using LUT muxes as long as SEL is static in all
clock domains. Now, what would be the best way to cut all timing analysis
from the input clocks to the output clock? Of course I also want to specify
a new period on the output clock (preferably without routing it outside the
chip and back).

---
entity clkmux8 is
Port
(
CLK0 : in std_logic:='0';
CLK1 : in std_logic:='0';
CLK2 : in std_logic:='0';
CLK3 : in std_logic:='0';
CLK4 : in std_logic:='0';
CLK5 : in std_logic:='0';
CLK6 : in std_logic:='0';
CLK7 : in std_logic:='0';
SEL : in std_logic_vector(2 downto 0);
CLKOUT : out std_logic
);
end clkmux8;

[...blabla...]

mux10:MUXCY port map (S=>SEL(0),O=>tclk10,CI=>CLK1,DI=>CLK0);
mux11:MUXCY port map (S=>SEL(0),O=>tclk11,CI=>CLK3,DI=>CLK2);
mux12:MUXCY port map (S=>SEL(0),O=>tclk12,CI=>CLK5,DI=>CLK4);
mux13:MUXCY port map (S=>SEL(0),O=>tclk13,CI=>CLK7,DI=>CLK6);

mux20:MUXCY port map (S=>SEL(1),O=>tclk20,CI=>tclk11,DI=>tclk10);
mux21:MUXCY port map (S=>SEL(1),O=>tclk21,CI=>tclk13,DI=>tclk12);

mux30:MUXCY port map (S=>SEL(2),O=>CLKOUT,CI=>tclk21,DI=>tclk20);

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