As mentioned in the datasheet, I've implemented in software SPI protocol
with CPOL=0, CPHA=1 (clock active low, shift data out on the falling SCLK
edge). The problem is that on DAC update only channel A is updated and only
values 2^n-1 (1, 3,..., 127,...1023, 2047, 4095) are accepted. Even commands
(like 'reset') are not executed. I even tried different versions of the
protocol (allways shifting on falling SCLK edge) but without any success.
LDAC pin is permanently tied low.
Datasheet mentions (in timing diagram) that all values are specified with
tr=tf=5ns. I don't know if this is the constraint, as in my case rise and
fall times are more than 50 ns.
DAC behaviour is really strange... and I'm out of ideas what may me wrong.
Damir
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:pbcrq1t45ehj61evv5b1o4lmfu47vldt6f@4ax.com...
On Sat, 24 Dec 2005 15:18:28 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
Hi,
Did anyone used this (or similar) DAC from Analog Devices.
I have severe communication protocol problems - I've implemented several
software versions, attached it to SPI - and I cannot get channels to
update
correctly or to send commands.
Damir
Yes, similar and without problems. It's hard to give more help than
that with what little information you have provided. Sorry.
--
Dan Henry