Hi,
Did anyone used this (or similar) DAC from Analog Devices.
I have severe communication protocol problems - I've implemented several
software versions, attached it to SPI - and I cannot get channels to update
correctly or to send commands.
Damir
Experience with AD5328 DAC
8 posts
• Page 1 of 1
Re: Experience with AD5328 DAC
by Dan Henry » Sun Dec 25, 2005 1:15 am
On Sat, 24 Dec 2005 15:18:28 +0100, "damir" <dzagar@BRISIsrce.hr>
wrote:
Yes, similar and without problems. It's hard to give more help than
that with what little information you have provided. Sorry.
--
Dan Henry
wrote:
Hi,
Did anyone used this (or similar) DAC from Analog Devices.
I have severe communication protocol problems - I've implemented several
software versions, attached it to SPI - and I cannot get channels to update
correctly or to send commands.
Damir
Yes, similar and without problems. It's hard to give more help than
that with what little information you have provided. Sorry.
--
Dan Henry
- Dan Henry
Re: Experience with AD5328 DAC
by damir » Mon Dec 26, 2005 9:15 am
As mentioned in the datasheet, I've implemented in software SPI protocol
with CPOL=0, CPHA=1 (clock active low, shift data out on the falling SCLK
edge). The problem is that on DAC update only channel A is updated and only
values 2^n-1 (1, 3,..., 127,...1023, 2047, 4095) are accepted. Even commands
(like 'reset') are not executed. I even tried different versions of the
protocol (allways shifting on falling SCLK edge) but without any success.
LDAC pin is permanently tied low.
Datasheet mentions (in timing diagram) that all values are specified with
tr=tf=5ns. I don't know if this is the constraint, as in my case rise and
fall times are more than 50 ns.
DAC behaviour is really strange... and I'm out of ideas what may me wrong.
Damir
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:pbcrq1t45ehj61evv5b1o4lmfu47vldt6f@4ax.com...
with CPOL=0, CPHA=1 (clock active low, shift data out on the falling SCLK
edge). The problem is that on DAC update only channel A is updated and only
values 2^n-1 (1, 3,..., 127,...1023, 2047, 4095) are accepted. Even commands
(like 'reset') are not executed. I even tried different versions of the
protocol (allways shifting on falling SCLK edge) but without any success.
LDAC pin is permanently tied low.
Datasheet mentions (in timing diagram) that all values are specified with
tr=tf=5ns. I don't know if this is the constraint, as in my case rise and
fall times are more than 50 ns.
DAC behaviour is really strange... and I'm out of ideas what may me wrong.
Damir
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:pbcrq1t45ehj61evv5b1o4lmfu47vldt6f@4ax.com...
On Sat, 24 Dec 2005 15:18:28 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
Hi,
Did anyone used this (or similar) DAC from Analog Devices.
I have severe communication protocol problems - I've implemented several
software versions, attached it to SPI - and I cannot get channels to
update
correctly or to send commands.
Damir
Yes, similar and without problems. It's hard to give more help than
that with what little information you have provided. Sorry.
--
Dan Henry
- damir
Re: Experience with AD5328 DAC
by Dan Henry » Mon Dec 26, 2005 5:15 pm
On Mon, 26 Dec 2005 09:43:48 +0100, "damir" <dzagar@BRISIsrce.hr>
wrote:
Perhaps a framing problem -- what about the SYNC signal?
--
Dan Henry
wrote:
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:pbcrq1t45ehj61evv5b1o4lmfu47vldt6f@4ax.com...
On Sat, 24 Dec 2005 15:18:28 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
Hi,
Did anyone used this (or similar) DAC from Analog Devices.
I have severe communication protocol problems - I've implemented several
software versions, attached it to SPI - and I cannot get channels to
update
correctly or to send commands.
Damir
Yes, similar and without problems. It's hard to give more help than
that with what little information you have provided. Sorry.
As mentioned in the datasheet, I've implemented in software SPI protocol
with CPOL=0, CPHA=1 (clock active low, shift data out on the falling SCLK
edge). The problem is that on DAC update only channel A is updated and only
values 2^n-1 (1, 3,..., 127,...1023, 2047, 4095) are accepted. Even commands
(like 'reset') are not executed. I even tried different versions of the
protocol (allways shifting on falling SCLK edge) but without any success.
LDAC pin is permanently tied low.
Datasheet mentions (in timing diagram) that all values are specified with
tr=tf=5ns. I don't know if this is the constraint, as in my case rise and
fall times are more than 50 ns.
DAC behaviour is really strange... and I'm out of ideas what may me wrong.
Perhaps a framing problem -- what about the SYNC signal?
--
Dan Henry
- Dan Henry
Re: Experience with AD5328 DAC
by Dan Henry » Mon Dec 26, 2005 5:15 pm
On Mon, 26 Dec 2005 09:24:12 -0700, Dan Henry <usenet@danlhenry.com>
wrote:
Also, I'd shift data out of the master on the rising edge so the data
is ready for the slave (DAC) to shift in on the falling edge.
--
Dan Henry
wrote:
On Mon, 26 Dec 2005 09:43:48 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:pbcrq1t45ehj61evv5b1o4lmfu47vldt6f@4ax.com...
On Sat, 24 Dec 2005 15:18:28 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
Hi,
Did anyone used this (or similar) DAC from Analog Devices.
I have severe communication protocol problems - I've implemented several
software versions, attached it to SPI - and I cannot get channels to
update
correctly or to send commands.
Damir
Yes, similar and without problems. It's hard to give more help than
that with what little information you have provided. Sorry.
As mentioned in the datasheet, I've implemented in software SPI protocol
with CPOL=0, CPHA=1 (clock active low, shift data out on the falling SCLK
edge). The problem is that on DAC update only channel A is updated and only
values 2^n-1 (1, 3,..., 127,...1023, 2047, 4095) are accepted. Even commands
(like 'reset') are not executed. I even tried different versions of the
protocol (allways shifting on falling SCLK edge) but without any success.
LDAC pin is permanently tied low.
Datasheet mentions (in timing diagram) that all values are specified with
tr=tf=5ns. I don't know if this is the constraint, as in my case rise and
fall times are more than 50 ns.
DAC behaviour is really strange... and I'm out of ideas what may me wrong.
Perhaps a framing problem -- what about the SYNC signal?
Also, I'd shift data out of the master on the rising edge so the data
is ready for the slave (DAC) to shift in on the falling edge.
--
Dan Henry
- Dan Henry
Re: Experience with AD5328 DAC
by Rich Webb » Mon Dec 26, 2005 11:41 pm
On Mon, 26 Dec 2005 09:43:48 +0100, "damir" <dzagar@BRISIsrce.hr> wrote:
I haven't used the AD part but I am working with a similar one from TI,
the TLV5628.
It's almost impossible to troubleshoot SPI without looking at the actual
timing. Any chance that you could grab a screen shot and post it to
alt.binaries.schematics.electronic?
You can use a two channel scope if you really have to, by walking up and
down the signals pair-wise, but a logic analyzer makes it much, much
easier.
The Ant8 or Ant16 from Rocky Logic www.rockylogic.com [1] aren't too
expensive and either would do the trick. I used an Ant8 from right when
they became available as a portable, stick-it-in-the-laptop-bag tester.
Recently sold it and got a LogicPort device that I've been very happy
with: http://www.pctestinstruments.com/. Very rarely ever use the boat
anchor "real" logic analyzer in the lab any more.
[1] Their server is reporting 403 Forbidden today. Don't know what's up
with that.
--
Rich Webb Norfolk, VA
DAC behaviour is really strange... and I'm out of ideas what may me wrong.
I haven't used the AD part but I am working with a similar one from TI,
the TLV5628.
It's almost impossible to troubleshoot SPI without looking at the actual
timing. Any chance that you could grab a screen shot and post it to
alt.binaries.schematics.electronic?
You can use a two channel scope if you really have to, by walking up and
down the signals pair-wise, but a logic analyzer makes it much, much
easier.
The Ant8 or Ant16 from Rocky Logic www.rockylogic.com [1] aren't too
expensive and either would do the trick. I used an Ant8 from right when
they became available as a portable, stick-it-in-the-laptop-bag tester.
Recently sold it and got a LogicPort device that I've been very happy
with: http://www.pctestinstruments.com/. Very rarely ever use the boat
anchor "real" logic analyzer in the lab any more.
[1] Their server is reporting 403 Forbidden today. Don't know what's up
with that.
--
Rich Webb Norfolk, VA
- Rich Webb
Re: Experience with AD5328 DAC
by damir » Wed Dec 28, 2005 5:15 pm
Sync is stable low before first clock high-to-low transition, and goes high
after last clock.
I shift out (change) data while SCLK is high and data is stable for 500 ns
before SCLK falling edge - I will try to change protocol and change data on
the SDA line at the SCLK rising edge - but I doubt that this will make any
change.
I will also try to capture screens from the scope and post images on the
binaries group.
Thanks for help - to you and Rich!
Damir
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:2160r1htg28s2gmd5u4n6dqn8gnd21el6n@4ax.com...
after last clock.
I shift out (change) data while SCLK is high and data is stable for 500 ns
before SCLK falling edge - I will try to change protocol and change data on
the SDA line at the SCLK rising edge - but I doubt that this will make any
change.
I will also try to capture screens from the scope and post images on the
binaries group.
Thanks for help - to you and Rich!
Damir
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:2160r1htg28s2gmd5u4n6dqn8gnd21el6n@4ax.com...
On Mon, 26 Dec 2005 09:43:48 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:pbcrq1t45ehj61evv5b1o4lmfu47vldt6f@4ax.com...
On Sat, 24 Dec 2005 15:18:28 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
Hi,
Did anyone used this (or similar) DAC from Analog Devices.
I have severe communication protocol problems - I've implemented several
software versions, attached it to SPI - and I cannot get channels to
update
correctly or to send commands.
Damir
Yes, similar and without problems. It's hard to give more help than
that with what little information you have provided. Sorry.
As mentioned in the datasheet, I've implemented in software SPI protocol
with CPOL=0, CPHA=1 (clock active low, shift data out on the falling SCLK
edge). The problem is that on DAC update only channel A is updated and
only
values 2^n-1 (1, 3,..., 127,...1023, 2047, 4095) are accepted. Even
commands
(like 'reset') are not executed. I even tried different versions of the
protocol (allways shifting on falling SCLK edge) but without any success.
LDAC pin is permanently tied low.
Datasheet mentions (in timing diagram) that all values are specified with
tr=tf=5ns. I don't know if this is the constraint, as in my case rise and
fall times are more than 50 ns.
DAC behaviour is really strange... and I'm out of ideas what may me wrong.
Perhaps a framing problem -- what about the SYNC signal?
--
Dan Henry
- damir
Re: Experience with AD5328 DAC
by Dan Henry » Thu Dec 29, 2005 9:15 am
On Wed, 28 Dec 2005 17:48:01 +0100, "damir" <dzagar@BRISIsrce.hr>
wrote:
Please post here saying that you did. Of my two Usenet access means,
one does not allow access to the alt.* groups. I would like to know
if/when to look for scope captures.
--
Dan Henry
wrote:
Sync is stable low before first clock high-to-low transition, and goes high
after last clock.
I shift out (change) data while SCLK is high and data is stable for 500 ns
before SCLK falling edge - I will try to change protocol and change data on
the SDA line at the SCLK rising edge - but I doubt that this will make any
change.
I will also try to capture screens from the scope and post images on the
binaries group.
Please post here saying that you did. Of my two Usenet access means,
one does not allow access to the alt.* groups. I would like to know
if/when to look for scope captures.
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:2160r1htg28s2gmd5u4n6dqn8gnd21el6n@4ax.com...
On Mon, 26 Dec 2005 09:43:48 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
"Dan Henry" <usenet@danlhenry.com> wrote in message
news:pbcrq1t45ehj61evv5b1o4lmfu47vldt6f@4ax.com...
On Sat, 24 Dec 2005 15:18:28 +0100, "damir" <dzagar@BRISIsrce.hr
wrote:
Hi,
Did anyone used this (or similar) DAC from Analog Devices.
I have severe communication protocol problems - I've implemented several
software versions, attached it to SPI - and I cannot get channels to
update
correctly or to send commands.
Damir
Yes, similar and without problems. It's hard to give more help than
that with what little information you have provided. Sorry.
As mentioned in the datasheet, I've implemented in software SPI protocol
with CPOL=0, CPHA=1 (clock active low, shift data out on the falling SCLK
edge). The problem is that on DAC update only channel A is updated and
only
values 2^n-1 (1, 3,..., 127,...1023, 2047, 4095) are accepted. Even
commands
(like 'reset') are not executed. I even tried different versions of the
protocol (allways shifting on falling SCLK edge) but without any success.
LDAC pin is permanently tied low.
Datasheet mentions (in timing diagram) that all values are specified with
tr=tf=5ns. I don't know if this is the constraint, as in my case rise and
fall times are more than 50 ns.
DAC behaviour is really strange... and I'm out of ideas what may me wrong.
Perhaps a framing problem -- what about the SYNC signal?
--
Dan Henry
--
Dan Henry
- Dan Henry
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