| Author |
Message |
Guest
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 Posted:
Sat Dec 24, 2005 5:15 pm Post subject:
XILINX I2C controller core in FPGA and multisource problem. |
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Has anyone implemented the I2C controller core mentioned in the xapp333
in a FPGA.
I have simulated the core to set the address register. and it works in
simulation. when i try to that there are problems during synthesis. i
think its got something to do with dual INPUTOUTPUT ports.
The synthesis tool keeps saying there are multisources and because of
which i think something has gone wrong with the DTACK signal and there
are problems.
I have pasted the part from synthesis report because of which i think
the problems arise.
meanwhile if anyone else has implemented the I2C controller core and
could give me tips it would be really helpful.
Thanks in advance
vasu
WARNING:Xst:2040 - Unit i2c_tb: 8 multi-source signals are replaced by
logic (pull-up yes): data_bus<0>, data_bus<1>, data_bus<2>,
data_bus<3>, data_bus<4>, data_bus<5>, data_bus<6>, data_bus<7>.
WARNING:Xst:2042 - Unit uC_interface: 9 internal tristates are replaced
by logic (pull-up yes): data_bus<0>, data_bus<1>, data_bus<2>,
data_bus<3>, data_bus<4>, data_bus<5>, data_bus<6>, data_bus<7>, irq.
WARNING:Xst:2183 - Unit i2c_control: the following tristate(s) are NOT
replaced by logic (Please refer to Answer Record 20048 for more
information): scl, sda.
WARNING:Xst:1906 - Unit uC_interface is merged (output ports from
interface drive multi-sources) |
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Guest
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| Posted:
Mon Dec 26, 2005 4:45 pm Post subject:
Re: XILINX I2C controller core in FPGA and multisource probl |
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Hi,
I have implemented a I2C bus core by myself.
When reading, a multiple source 'error' would happen if your code
assertes the acknowledge bit slightly earlier than the target deasserts
the bus from the last read data bit or when writing, if your code
deasserts the acknowledge bit slightly later than the target asserts
the acknowledge bit on the bus.
You may ignore them totally without any problem.
Weng |
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Antti Lukats
Guest
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| Posted:
Mon Dec 26, 2005 5:15 pm Post subject:
Re: XILINX I2C controller core in FPGA and multisource probl |
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<wtxwtx@gmail.com> schrieb im Newsbeitrag
news:1135593905.451170.291220@f14g2000cwb.googlegroups.com...
| Quote: | Hi,
I have implemented a I2C bus core by myself.
When reading, a multiple source 'error' would happen if your code
assertes the acknowledge bit slightly earlier than the target deasserts
the bus from the last read data bit or when writing, if your code
deasserts the acknowledge bit slightly later than the target asserts
the acknowledge bit on the bus.
You may ignore them totally without any problem.
Weng
http://xilant.com/content/view/31/55/ |
Weng, the multipy source error is usually fatal synthesis error and prevents
the bitstream generation until fixed.
the OP has problem wiring up the processor data bus, not the SDA/SCL lines
IMHO
Antti |
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Guest
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| Posted:
Mon Dec 26, 2005 5:15 pm Post subject:
Re: XILINX I2C controller core in FPGA and multisource probl |
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Hi Antti,
Thank you for indicating my wrong answer.
I misunderstood the problem.
One of errors is multi-source data_bus(7 downto 0) are assigned in more
than one processes!
It is easy to correct it:
Use search key to search signal 'data_bus' through the module source
file and see how many times the data_bus are assigned. Put all
assignments in one process only.
Weng |
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Antti Lukats
Guest
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| Posted:
Mon Dec 26, 2005 5:15 pm Post subject:
Re: XILINX I2C controller core in FPGA and multisource probl |
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<wtxwtx@gmail.com> schrieb im Newsbeitrag
news:1135599779.396787.40140@g14g2000cwa.googlegroups.com...
| Quote: | Hi Antti,
Thank you for indicating my wrong answer.
I misunderstood the problem.
One of errors is multi-source data_bus(7 downto 0) are assigned in more
than one processes!
It is easy to correct it:
Use search key to search signal 'data_bus' through the module source
file and see how many times the data_bus are assigned. Put all
assignments in one process only.
Weng
Weng you are a bit mistaken again the data_bus is assigned once outside |
process
data_bus <= data_out when (r_w = '1' and dtack_oe = '1') else (others =>
'Z');
in the uc_interface.vhd
so the ip-core is 100% proper for its intended function - controller for
external microcontroller.
for on-chip soc bus, the uc_interface module should be replaced, or
modified.
antti |
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Guest
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| Posted:
Tue Dec 27, 2005 1:15 am Post subject:
Re: XILINX I2C controller core in FPGA and multisource probl |
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Hi Antti,
I don't have his source code and made a judgement based on the
following warnings:
Unit i2c_tb: 8 multi-source signals are replaced by
logic (pull-up yes): data_bus<0>, data_bus<1>, data_bus<2>,
data_bus<3>, data_bus<4>, data_bus<5>, data_bus<6>, data_bus<7>.
1. data_bus are multi-source signals;
2. data_bus is in the module: i2c_tb. It may be in his test bench code
to make the multi-source error.
I never claimed that it was the IP code error. Any IP code never makes
such basic and fundamental error.
Weng |
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Antti Lukats
Guest
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| Posted:
Tue Dec 27, 2005 9:15 am Post subject:
Re: XILINX I2C controller core in FPGA and multisource probl |
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<wtxwtx@gmail.com> schrieb im Newsbeitrag
news:1135640060.426695.311280@g44g2000cwa.googlegroups.com...
| Quote: | Hi Antti,
I don't have his source code and made a judgement based on the
following warnings:
Unit i2c_tb: 8 multi-source signals are replaced by
logic (pull-up yes): data_bus<0>, data_bus<1>, data_bus<2>,
data_bus<3>, data_bus<4>, data_bus<5>, data_bus<6>, data_bus<7>.
1. data_bus are multi-source signals;
2. data_bus is in the module: i2c_tb. It may be in his test bench code
to make the multi-source error.
I never claimed that it was the IP code error. Any IP code never makes
such basic and fundamental error.
Weng
no problems - I just checked the original - form without doing that your |
guess was 'close'
antti |
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