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Would it be possible for PowerPC to evolve out of using
segmentation? For 32-bit PPC implementations, providing 16
segment registers allows for simple, fast translation of
effective addresses to virtual addresses; but for 64-bit
implementations segmentation forces the use of a segment cache
with a required tag check delaying access (assuming it is not
direct-mapped) to a TLB. The use of Effective-to-Real Address
Translation (ERAT) caches helps (especially with Process IDs in
the tags), but extending 64-bit effective addresses to 80-bit
virtual addresses does not seem worth an additional layer of
translation when accessing TLBs.

(Even for IPF, it is not clear to me that the region registers'
extension of the virtual address is particularly useful. For a
single-address-space OS, such does not provide convenient
portable pointers which are the main advantage of a SASOS. For a
conventional OS, region registers' VA extension might provide a
convenient means of allocating thread-local storage that is
protected from other threads [on a thread switch only the TLS
region register would be changed] and for providing a common OS
data region [i.e., one region register would be shared by all
contexts]. Can someone cure my ignorance by explaining the
reasons behind providing eight region registers? I suppose such
might also be used to provide regions with different default page
sizes, which is the only way that linear page tables can be used
with multiple page sizes.)

Paul A. Clayton
just a technophile

<Dysthymicdolt@aol.com> wrote:

Would it be possible for PowerPC to evolve out of using
segmentation? For 32-bit PPC implementations, providing 16
segment registers allows for simple, fast translation of
effective addresses to virtual addresses; but for 64-bit
implementations segmentation forces the use of a segment cache
with a required tag check delaying access (assuming it is not
direct-mapped) to a TLB. The use of Effective-to-Real Address
Translation (ERAT) caches helps (especially with Process IDs in
the tags), but extending 64-bit effective addresses to 80-bit
virtual addresses does not seem worth an additional layer of
translation when accessing TLBs.

POWER5+ added support for 1 TB segments and multiple pagesizes in a
segment. That pretty much allows turning off segmentation if you want.

--
Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark

Niels Jørgen Kruse wrote:

POWER5+ added support for 1 TB segments and multiple pagesizes in a
segment. That pretty much allows turning off segmentation if you want.

That still leaves the SLB-access (which is likely to be a hit with
1TiB segments) as a step before the TLBs can be accessed
and the use of ERATs rather than L1 TLBs. (Do the ERATs
have to be flushed on a context switch or is an ASID included?)
ISTM that segmentation is not partiicularly useful and it would
be relatively easy to discard given that it is not supposed to be
visible to applications.

BTW, where did you get this POWER5+ information? Google
wasn't particularly helpful with: POWER5+ segment


Paul A. Clayton
just a technophile

<Dysthymicdolt@aol.com> wrote:

Niels Jørgen Kruse wrote:
POWER5+ added support for 1 TB segments and multiple pagesizes in a
segment. That pretty much allows turning off segmentation if you want.

That still leaves the SLB-access (which is likely to be a hit with
1TiB segments) as a step before the TLBs can be accessed
and the use of ERATs rather than L1 TLBs. (Do the ERATs
have to be flushed on a context switch or is an ASID included?)
ISTM that segmentation is not partiicularly useful and it would
be relatively easy to discard given that it is not supposed to be
visible to applications.

Only ERAT access is performance critical. I haven't seen information on
ASID, but obviously some provision has to have been made to run threads
from different processes on an SMT.

BTW, where did you get this POWER5+ information? Google
wasn't particularly helpful with: POWER5+ segment

The information is on page 10 of "IBM IntelliStation POWER 285 Technical
Overview and Introduction". I can mail you a copy if you don't google it
down easily.

--
Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark

""Niels Jørgen Kruse"" <nospam@ab-katrinedal.dk> wrote in message
news:1h88bl7.6rds2i1j6np8gN%nospam@ab-katrinedal.dk...

Dysthymicdolt@aol.com> wrote:

Niels Jørgen Kruse wrote:
POWER5+ added support for 1 TB segments and multiple pagesizes in a
segment. That pretty much allows turning off segmentation if you
want.

That still leaves the SLB-access (which is likely to be a hit with
1TiB segments) as a step before the TLBs can be accessed
and the use of ERATs rather than L1 TLBs. (Do the ERATs
have to be flushed on a context switch or is an ASID included?)
ISTM that segmentation is not partiicularly useful and it would
be relatively easy to discard given that it is not supposed to be
visible to applications.

Only ERAT access is performance critical. I haven't seen information on
ASID, but obviously some provision has to have been made to run threads
from different processes on an SMT.

BTW, where did you get this POWER5+ information? Google
wasn't particularly helpful with: POWER5+ segment

The information is on page 10 of "IBM IntelliStation POWER 285
Technical
Overview and Introduction". I can mail you a copy if you don't google
it
down easily.

--
Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark

Just let me add that there are basically two sites for IBM documentation.
The publications site in boulder, and the ITSO Redbook site in Pok. The
former has all the official manuals and stuff. The latter has additional
user oriented books.

Niels Jørgen Kruse wrote:

Dysthymicdolt@aol.com> wrote:

Only ERAT access is performance critical. I haven't seen information on
ASID, but obviously some provision has to have been made to run threads
from different processes on an SMT.

Agreed, but it is a bit of a wart and ISTR that ERATs get
flushed on context switches (probably from the PPC750
user's guide). SMT would only require a virtual processor
ID (one bit in POWER5) not a ASID.

BTW, where did you get this POWER5+ information? Google
wasn't particularly helpful with: POWER5+ segment

The information is on page 10 of "IBM IntelliStation POWER 285 Technical
Overview and Introduction". I can mail you a copy if you don't google it
down easily.

Thanks! With the document title google came through.

Dysthymicdolt@aol.com wrote:

Niels Jørgen Kruse wrote:

POWER5+ added support for 1 TB segments and multiple pagesizes in a
segment. That pretty much allows turning off segmentation if you want.


That still leaves the SLB-access (which is likely to be a hit with
1TiB segments) as a step before the TLBs can be accessed
and the use of ERATs rather than L1 TLBs. (Do the ERATs
have to be flushed on a context switch or is an ASID included?)
ISTM that segmentation is not partiicularly useful and it would
be relatively easy to discard given that it is not supposed to be
visible to applications.
Well I'm a little out of date (with respect to P5/P5+/P6 plus its all a

little foggy now), but back a few years ago when I was whining about how
crappy and useless the PPC segmentation model was (I wanted segments
with programmable size limits if any at all) I was told that the
segments on the PPC were very useful because it was quicker to flip a
few segment registers on context switch than to flush the TLB. From what
I understand this could still hold true because the TLB's are virtual to
real (not effective to real) and now you just flush the SLB. The VSIDs
can continue to be unique between different contexts. Of course the
question is how slow is flushing the SLB and reloading it vs just doing
a TLB flush.
Anyway, I think the ERAT's use the class value from the SLB's to
control when they get flushed. Of course its only 1 bit, so your sort of
stuck with local vs global segments.
Personally, the whole SLB thing seems sort of a mess and some form of
context ID applied to the top of the EA would work just as well, except
in environments where there are big regions of shared memory that are
mapping to the same VSID. The extra TLB stress with a context ID might
slow those environments down if everyone was using little pages. Since
this is probably an important market for IBM (big shared memory model
programs) i'm betting you won't see them make that change in the near
future.
But, on the other hand they probably would make the class bit a larger
field or just put a context ID on the top of the ESID so that they can
do selective flushing of the SLB and therefore any future ERATS. Plus
there is the possibility they already did it only the hypervisors
control it on a partition by partion basis and its completely invisible.

<Dysthymicdolt@aol.com> wrote:

Niels Jørgen Kruse wrote:
Dysthymicdolt@aol.com> wrote:

Only ERAT access is performance critical. I haven't seen information on
ASID, but obviously some provision has to have been made to run threads
from different processes on an SMT.

Agreed, but it is a bit of a wart and ISTR that ERATs get
flushed on context switches (probably from the PPC750
user's guide). SMT would only require a virtual processor
ID (one bit in POWER5) not a ASID.

You must be thinking of the 970, not the 750. The 750 has no ERAT: the
32KB L1 is 8 way associative, so it can be indexed with untranslated
bits. The TLBs are 2 way associative and can be indexed with bits
untranslated by segments, ie. you access TLB in parallel with segment
register access.

--
Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark