Brad Smallridge
Guest
|
 Posted:
Tue Dec 27, 2005 9:15 am Post subject:
Re: Xilinx V4 LVDS |
|
|
"avishay" <avishorp@yahoo.com> wrote in message
news:1135664159.180738.57490@g44g2000cwa.googlegroups.com...
| Quote: | Hi Brad
Are you sure you're decoding Camera Link correctly? Both Channel Link
and Camera Link mangle the bit order on the stream, so make sure you'r
looking at the correct bit.
Avishay
|
I hope so. I have a counter and a mux routing all the signals in turn to an
LED that I scope. There is nothing that indicates to me that a DVAL=1 or an
LVAL exist on the X2 stream. I have checked the operation of the camera
with another board that has National LVDS chips and the camera seems to be
operating OK in base configuration, 12 bit, one tap mode.
Channel X0
Bit 0 ChanLink 0 CamLink 0
Bit 1 ChanLink 1 CamLink 1
Bit 2 ChanLink 2 CamLink 2
Bit 3 ChanLink 3 CamLink 3
Bit 4 ChanLink 4 CamLink 4
Bit 5 ChanLink 6 CamLink 5
Bit 6 ChanLink 7 CamLink 8
Channel X1
Bit 0 ChanLink 8 CamLink 9
Bit 1 ChanLink 9 CamLink 10
Bit 2 ChanLink 12 CamLink 11
Bit 3 ChanLink 13
Bit 4 ChanLink 14
Bit 5 ChanLink 15
Bit 6 ChanLink 18
Channel X2
Bit 0 ChanLink 19
Bit 1 ChanLink 20
Bit 2 ChanLink 21
Bit 3 ChanLink 22
Bit 4 ChanLink 24 CamLink LVAL
Bit 5 ChanLink 25
Bit 6 ChanLink 26 CamLink DVAL
Channel X3
Bit 0 ChanLink 27 CamLink 6
Bit 1 ChanLink 5 CamLink 7
Bit 2 ChanLink 10
Bit 3 ChanLink 11
Bit 4 ChanLink 16
Bit 5 ChanLink 17
Bit 6 ChanLink 23
By adding about 50 delay taps to the 140_280 dcm and 4 clock cycles to the
xclk clkdiv signal, I have been able to get a video looking signal,
simultaneously, into all the camlink data positions, except the DVAL and
LVAL. I must admit however that the first and second bits look very similar
on the scope as if they were the same value. All the unmarked signals are
zero.
I have put some of the code below. This is work in progress because I have
begun to play around by fixed IDELAY to the X0 ISERDES. I don't know what is
better, to delay the signals coming into the ISERDESs or delay the clkdiv
strobe.
reset1 <= not sys_rst_in;
cam1_dcmfx: cam1_40_140
port map(
clkin_n_in => cam1_in(6), -- 40 MHz
clkin_p_in => cam1_in(7), -- Differential pair
rst_in => reset1,
clkfx_out => cam1_clk7xdiv2, -- 140MHz
clkin_ibufgds_out => open,
clk0_out => cam1_xclk_0, -- 40 MHz
locked_out => cam1_lock7xdiv2 );
reset_delay_SRL16 : SRL16
generic map (
INIT => X"0000")
port map (
Q => reset2,
A0 => '1', -- 16 clock delays
A1 => '1',
A2 => '1',
A3 => '1',
CLK => cam1_clk7xdiv2,
D => cam1_lock7xdiv2 );
reset3 <= not( cam1_lock7xdiv2 and reset2 );
-- added 20 units of phase delay
cam1_dcm2x: cam1_140_280
port map(
clkin_in => cam1_clk7xdiv2, -- 140 MHz
rst_in => reset3, -- from SRL16
clk0_out => open,
clk2x_out => cam1_clk7x, -- 280 MHz
locked_out => cam1_lock7x );
xclk_delay_process: process(cam1_clk7x)
begin
if( cam1_clk7x'event and cam1_clk7x='1' ) then
cam1_xclk_1 <= cam1_xclk_0;
cam1_xclk_2 <= cam1_xclk_1;
cam1_xclk_3 <= cam1_xclk_2;
cam1_xclk_4 <= cam1_xclk_3;
end if;
end process;
xclk_bufg: BUFG
port map(
O => cam1_xclk,
I => cam1_xclk_4 );
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output indicates validity of the REFCLK
REFCLK => cam1_clk7x, -- 1-bit reference clock input
RST => reset3 ); -- 1-bit reset input
--------------------------------------------------------------------------
-- Camera Link Deserializers
--
-- Each of the four serial streams X0 X1 X2 and X3
-- have a pair of differential inputs _n and _p
-- attached to the gpio_exp_hdr2 (General Purpose Input Output Header 2 )
-- that must be reconciled with an IBUFDS (Input BUFfer Differential Swing)
-- The resulting signal is fed to a pair of Master and Slave
-- ISERDES (Input SERializer DESerializer).
cam1_x0_ibufd_inst : IBUFDS
port map (
O => cam1_x0,
I => cam1_in(1),
IB => cam1_in(0) );
x0_iserdes_master : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- DDR SDR
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
-- IOBDELAY => "NONE", -- delay chain
"NONE","IBUF","IFD","BOTH"
-- IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
-- IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
IOBDELAY => "BOTH", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "FIXED", -- tap delay "DEFAULT", "FIXED","VARIABLE"
IOBDELAY_VALUE => 61, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => cam1_x0_bit(0),
Q2 => cam1_x0_bit(1),
Q3 => cam1_x0_bit(2),
Q4 => cam1_x0_bit(3),
Q5 => cam1_x0_bit(4),
Q6 => cam1_x0_bit(5),
SHIFTOUT1 => cam1_x0_shift1,
SHIFTOUT2 => cam1_x0_shift2,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => cam1_x0,
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => reset3 );
x0_iserdes_slave : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- "DDR" "SDR"
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
-- IOBDELAY => "NONE", -- delay chain
"NONE","IBUF","IFD","BOTH"
-- IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
-- IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
IOBDELAY => "BOTH", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "FIXED", -- tap delay "DEFAULT", "FIXED","VARIABLE"
IOBDELAY_VALUE => 61, -- initial tap delay 0 to 63
NUM_CE => 2, -- clock enables 1,2
SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => open,
Q2 => open,
Q3 => cam1_x0_bit(6),
Q4 => open,
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => '0',
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => cam1_x0_shift1,
SHIFTIN2 => cam1_x0_shift2,
SR => reset3 );
---------------------------------------------------------------------------
cam1_x1_ibufd_inst : IBUFDS
port map (
O => cam1_x1,
I => cam1_in(3),
IB => cam1_in(2) );
x1_iserdes_master : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- DDR SDR
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => cam1_x1_bit(0),
Q2 => cam1_x1_bit(1),
Q3 => cam1_x1_bit(2),
Q4 => cam1_x1_bit(3),
Q5 => cam1_x1_bit(4),
Q6 => cam1_x1_bit(5),
SHIFTOUT1 => cam1_x1_shift1,
SHIFTOUT2 => cam1_x1_shift2,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => cam1_x1,
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => reset3 );
x1_iserdes_slave : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- "DDR" "SDR"
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 2, -- clock enables 1,2
SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => open,
Q2 => open,
Q3 => cam1_x1_bit(6),
Q4 => open,
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => '0',
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => cam1_x1_shift1,
SHIFTIN2 => cam1_x1_shift2,
SR => reset3 );
---------------------------------------------------------------------------
cam1_x2_ibufd_inst : IBUFDS
port map (
O => cam1_x2,
I => cam1_in(5),
IB => cam1_in(4) );
x2_iserdes_master : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- DDR SDR
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => cam1_x2_bit(0),
Q2 => cam1_x2_bit(1),
Q3 => cam1_x2_bit(2),
Q4 => cam1_x2_bit(3),
Q5 => cam1_x2_bit(4),
Q6 => cam1_x2_bit(5),
SHIFTOUT1 => cam1_x2_shift1,
SHIFTOUT2 => cam1_x2_shift2,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => cam1_x2,
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => reset3 );
x2_iserdes_slave : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- "DDR" "SDR"
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 2, -- clock enables 1,2
SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => open,
Q2 => open,
Q3 => cam1_x2_bit(6),
Q4 => open,
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => '0',
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => cam1_x2_shift1,
SHIFTIN2 => cam1_x2_shift2,
SR => reset3 );
----------------------------------------------------------------------------
cam1_x3_ibufd_inst : IBUFDS
port map (
O => cam1_x3,
I => cam1_in(9),
IB => cam1_in(8) );
x3_iserdes_master : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- DDR SDR
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT", "FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => cam1_x3_bit(0),
Q2 => cam1_x3_bit(1),
Q3 => cam1_x3_bit(2),
Q4 => cam1_x3_bit(3),
Q5 => cam1_x3_bit(4),
Q6 => cam1_x3_bit(5),
SHIFTOUT1 => cam1_x3_shift1,
SHIFTOUT2 => cam1_x3_shift2,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => cam1_x3,
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => reset3 );
x3_iserdes_slave : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- "DDR" "SDR"
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 2, -- clock enables 1,2
SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => open,
Q2 => open,
Q3 => cam1_x3_bit(6),
Q4 => open,
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => '0',
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => cam1_x3_shift1,
SHIFTIN2 => cam1_x3_shift2,
SR => reset3 );
cam1_bit( 0) <= cam1_x0_bit(0);
cam1_bit( 1) <= cam1_x0_bit(1);
cam1_bit( 2) <= cam1_x0_bit(2);
cam1_bit( 3) <= cam1_x0_bit(3);
cam1_bit( 4) <= cam1_x0_bit(4);
cam1_bit( 5) <= cam1_x0_bit(5);
cam1_bit( 6) <= cam1_x0_bit(6);
cam1_bit( 7) <= cam1_x1_bit(0);
cam1_bit( 8) <= cam1_x1_bit(1);
cam1_bit( 9) <= cam1_x1_bit(2);
cam1_bit(10) <= cam1_x1_bit(3);
cam1_bit(11) <= cam1_x1_bit(4);
cam1_bit(12) <= cam1_x1_bit(5);
cam1_bit(13) <= cam1_x1_bit(6);
cam1_bit(14) <= cam1_x2_bit(0);
cam1_bit(15) <= cam1_x2_bit(1);
cam1_bit(16) <= cam1_x2_bit(2);
cam1_bit(17) <= cam1_x2_bit(3);
cam1_bit(18) <= cam1_x2_bit(4);
cam1_bit(19) <= cam1_x2_bit(5);
cam1_bit(20) <= cam1_x2_bit(6);
cam1_bit(21) <= cam1_x3_bit(0);
cam1_bit(22) <= cam1_x3_bit(1);
cam1_bit(23) <= cam1_x3_bit(2);
cam1_bit(24) <= cam1_x3_bit(3);
cam1_bit(25) <= cam1_x3_bit(4);
cam1_bit(26) <= cam1_x3_bit(5);
cam1_bit(27) <= cam1_x3_bit(6);
-- Cameral Link is a special subset of the 28 lines above
led_test_counter_3_process:process(cam1_xclk)
begin
if( cam1_xclk'event and cam1_xclk='1') then
if( reset3='1' ) then
test_counter_3 <= (others=>'0');
test_counter_4 <= (others=>'0');
elsif( test_counter_3 = (test_counter_3'range => '1') ) then
test_counter_3 <= (others=>'0');
test_counter_4 <= test_counter_4+1;
else
test_counter_3 <= test_counter_3+1;
end if;
end if;
end process;
led_test0_process:process(cam1_xclk)
begin
if( cam1_xclk'event and cam1_xclk='1') then
if( reset3='1' ) then
gpio(0)<='0';
else
gpio(0)<=test_counter_4( 6);
end if;
end if;
end process;
led_test_counter_5_process:process(cam1_xclk)
begin
if( cam1_xclk'event and cam1_xclk='1') then
if( (test_counter_4(6)='1') and test_5='0' ) then
test_counter_5<= test_counter_5 +1;
elsif( test_counter_5 = 28 ) then
test_counter_5<= (others=>'0');
end if;
test_5 <= test_counter_4(6);
end if;
end process;
led1_out_process:process(test_counter_5)
begin
case test_counter_5 is
when "000000" => gpio(1) <= cam1_bit( 0);
when "000001" => gpio(1) <= cam1_bit( 1);
when "000010" => gpio(1) <= cam1_bit( 2);
when "000011" => gpio(1) <= cam1_bit( 3);
when "000100" => gpio(1) <= cam1_bit( 4);
when "000101" => gpio(1) <= cam1_bit( 5);
when "000110" => gpio(1) <= cam1_bit( 6);
when "000111" => gpio(1) <= cam1_bit( 7);
when "001000" => gpio(1) <= cam1_bit( 8);
when "001001" => gpio(1) <= cam1_bit( 9);
when "001010" => gpio(1) <= cam1_bit(10);
when "001011" => gpio(1) <= cam1_bit(11);
when "001100" => gpio(1) <= cam1_bit(12);
when "001101" => gpio(1) <= cam1_bit(13);
when "001110" => gpio(1) <= cam1_bit(14);
when "001111" => gpio(1) <= cam1_bit(15);
when "010000" => gpio(1) <= cam1_bit(16);
when "010001" => gpio(1) <= cam1_bit(17);
when "010010" => gpio(1) <= cam1_bit(18);
when "010011" => gpio(1) <= cam1_bit(19);
when "010100" => gpio(1) <= cam1_bit(20);
when "010101" => gpio(1) <= cam1_bit(21);
when "010110" => gpio(1) <= cam1_bit(22);
when "010111" => gpio(1) <= cam1_bit(23);
when "011000" => gpio(1) <= cam1_bit(24);
when "011001" => gpio(1) <= cam1_bit(25);
when "011010" => gpio(1) <= cam1_bit(26);
when "011011" => gpio(1) <= cam1_bit(27);
when others => gpio(1) <= '1';
end case;
end process;
gpio(2) <= cam1_bit(0);
gpio(3) <= cam1_bit(1);
| Quote: | Brad Smallridge wrote:
Hello,
Having trouble with some LVDS signals coming from a Camera Link
interface.
I expect to see from steady signals coming from this line camera. DVAL=1.
But it's not there. And the LVAL, line valid, only comes on for maybe one
clock, and I expect it to come on for 2K clocks.
I am using IBUFDS as inputs. The UCF file loc the pins but that is all.
Do
I need something more to drop the 100 ohm termination resitance?
Brad Smallridge
aivision.com
|
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