| Author |
Message |
Engine
Guest
|
 Posted:
Tue Dec 27, 2005 5:15 pm Post subject:
Xilinx Stepping Methodology |
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A friend send me a document link.
http://direct.xilinx.com/bvdocs/notifications/xcn05025.pdf
He suggest we do not select Virtex4 in our projects.
I am not sure the real meaning of this document.
Does it mean that there are three bugs in the step 1 Virtex4 LX/SX?
Why do not call the Step 2 LX/SX as the mass production LX/SX?
Are there still bugs in step 2 LX/SX?
Whether step 3 LX/SX will be relased later?
Why FX is in step 0 now, what's the defination of step 0?
Please help me!
If it is ture, I would like to use the old VirtexII or Stratix on my
projects.
Thanks,
Engine |
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Austin Lesea
Guest
|
| Posted:
Tue Dec 27, 2005 5:15 pm Post subject:
Re: Xilinx Stepping Methodology |
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Engine,
Well, we did not invent stepping, Intel did.
Stepping is just another way to keep track of what you are shipping.
Let me give you an example:
We go to production, even perhaps with errata:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14052
which is an example of an errata for Virtex 2 Pro.
Errata are items that are presently not working as they are described in
the documentation.
Errata can be cleared by: manual work-arounds with technical answers, or
product notices; changes to the silicon (very rare); changes to the
software (so that the problem is worked around automatically; and
everything works as documented); or changes to the data sheet (so that
the issue is described properly).
The stepping system ensures "backward compatibility" which means that
any future chips MUST work with older bitstreams, in older designs.
This means that the customer does not have to worry that a new mask
revision will cause all of your previous IP to suddenly be "broken" and
need to be regenerated!
Some other manufacturers are on their n-th revision of silicon, and have
no "stepping" system at all, nor any policy about what they are doing
(to you).
If anything, I would require a properly documented stepping policy for
approval of any component, so that I would be sure that I would not be
"surprised" in any future shipment.
To this end, Virtex 4 was one of the first products to have the fully
implemented stepping system in place. Eventually all products will use
the system.
As always, if your company has its own policies, with their own
requirements, Xilinx is more than willing to work with you to establish
your own required flow to meet those needs. Some examples are customers
who require samples of the new stepping, and need 90 days before the new
stepping is allowed to be shipped to them as production. These
requirements are quite common with automotive suppliers, for example.
If you have any other concerns or questions on stepping, please consult
your Xilinx FAE. As well, if you have any questions or concerns about
errata, also consult your FAE.
Austin
Engine wrote:
| Quote: | A friend send me a document link.
http://direct.xilinx.com/bvdocs/notifications/xcn05025.pdf
He suggest we do not select Virtex4 in our projects.
I am not sure the real meaning of this document.
Does it mean that there are three bugs in the step 1 Virtex4 LX/SX?
Why do not call the Step 2 LX/SX as the mass production LX/SX?
Are there still bugs in step 2 LX/SX?
Whether step 3 LX/SX will be relased later?
Why FX is in step 0 now, what's the defination of step 0?
Please help me!
If it is ture, I would like to use the old VirtexII or Stratix on my
projects.
Thanks,
Engine
|
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|
| Back to top |
|
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Ray Andraka
Guest
|
| Posted:
Tue Dec 27, 2005 5:15 pm Post subject:
Re: Xilinx Stepping Methodology |
|
|
Engine wrote:
| Quote: | A friend send me a document link.
http://direct.xilinx.com/bvdocs/notifications/xcn05025.pdf
He suggest we do not select Virtex4 in our projects.
I am not sure the real meaning of this document.
Does it mean that there are three bugs in the step 1 Virtex4 LX/SX?
Why do not call the Step 2 LX/SX as the mass production LX/SX?
Are there still bugs in step 2 LX/SX?
Whether step 3 LX/SX will be relased later?
Why FX is in step 0 now, what's the defination of step 0?
Please help me!
If it is ture, I would like to use the old VirtexII or Stratix on my
projects.
Thanks,
Engine
|
Think of the stepping number as service packs for the silicon. The
higher stepping numbers generally reflect silicon revisions to correct
deficiencies in earlier silicon. There aren't really any show-stopper
bugs in the V4 silicon, so I wouldn't discard a V4 solution jsut because
someone suggested you didn't use the parts.
Step 0 is the first silicon, which is/was sold as the engineering samples.
The NBTI problem mentioned in the link you posted turns out to be a
non-problem for real world designs. It does degrade DCM performance if
the DCMs are not operated according to the constraints listed, but the
DCM is so much faster than what is required to support the fabric, that
the degradation does not slow them enough to affect real-world designs.
IMHO, Xilinx did the right thing with regards to disseminating info
about the NBTI problem so that customers could work with all the info
known at the time rather than leaving the customer to potentially
discovering a problem on their own later (unlike the handling of the
FIFO16 issue).
The Virtex4 does have significant advantages over the earlier families.
As with most silicon rollouts of this complexity, there are some fairly
minor bugs in the design that will be worked out over time. The only one
I am aware of that is a show stopper is the MGT's in the FX line. If
that doesn't affect your design plans, there is no reason I can see to
avoid the V4 line. I've got a couple major V4SX55 designs working
satisfactorly in the lab now, and overall I am happy with the device. |
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Engine
Guest
|
| Posted:
Wed Dec 28, 2005 9:15 am Post subject:
Re: Xilinx Stepping Methodology |
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I think I can find way to avoid the existed bugs, but I do not know whether
there are any other bugs existed in step 2.
So thank you share your exp on SX55 with me.
Thanks,
Engine
"Ray Andraka" wrote:
| Quote: | Engine wrote:
A friend send me a document link.
http://direct.xilinx.com/bvdocs/notifications/xcn05025.pdf
He suggest we do not select Virtex4 in our projects.
I am not sure the real meaning of this document.
Does it mean that there are three bugs in the step 1 Virtex4 LX/SX?
Why do not call the Step 2 LX/SX as the mass production LX/SX?
Are there still bugs in step 2 LX/SX?
Whether step 3 LX/SX will be relased later?
Why FX is in step 0 now, what's the defination of step 0?
Please help me!
If it is ture, I would like to use the old VirtexII or Stratix on my
projects.
Thanks,
Engine
Think of the stepping number as service packs for the silicon. The higher
stepping numbers generally reflect silicon revisions to correct
deficiencies in earlier silicon. There aren't really any show-stopper
bugs in the V4 silicon, so I wouldn't discard a V4 solution jsut because
someone suggested you didn't use the parts.
Step 0 is the first silicon, which is/was sold as the engineering samples.
The NBTI problem mentioned in the link you posted turns out to be a
non-problem for real world designs. It does degrade DCM performance if
the DCMs are not operated according to the constraints listed, but the DCM
is so much faster than what is required to support the fabric, that the
degradation does not slow them enough to affect real-world designs. IMHO,
Xilinx did the right thing with regards to disseminating info about the
NBTI problem so that customers could work with all the info known at the
time rather than leaving the customer to potentially discovering a problem
on their own later (unlike the handling of the FIFO16 issue).
The Virtex4 does have significant advantages over the earlier families. As
with most silicon rollouts of this complexity, there are some fairly minor
bugs in the design that will be worked out over time. The only one I am
aware of that is a show stopper is the MGT's in the FX line. If that
doesn't affect your design plans, there is no reason I can see to avoid
the V4 line. I've got a couple major V4SX55 designs working satisfactorly
in the lab now, and overall I am happy with the device. |
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Austin Lesea
Guest
|
| Posted:
Wed Dec 28, 2005 5:15 pm Post subject:
Re: Xilinx Stepping Methodology |
|
|
Yes,
You see exactly what this means.
The advantage to us is that we go to production sooner (and our
customers get full production qualified parts sooner), and it allows us
to ship an initial stepping that may have some limitations, or bugs
(with the errata to describe them, with any workarounds, etc.).
But, when we fix the bugs, we must be sure that the new silicon can use
the older bitstreams compiled ealier, and be equivalent.
If the new software is used with a new stepping, then the new features
are then enabled.
One disadvantage is that the customer has to keep track of stepping of
material shipped if they wish to generate new bitstreams, and
reconfigure the parts that are already in the field. This should not be
an issue, as most companies already keep track of their shipped products
with revision controls, or issue numbers.
Austin
Engine wrote:
| Quote: | I see.
As the backward compatibility must be executed in silicon level, not
software level, I guess it will be a challenge job for your team.
:-)
Thank you very much!
Engine
Austin Lesea wrote,
Engine,
Well, we did not invent stepping, Intel did.
Stepping is just another way to keep track of what you are shipping.
Let me give you an example:
We go to production, even perhaps with errata:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14052
which is an example of an errata for Virtex 2 Pro.
Errata are items that are presently not working as they are described in
the documentation.
Errata can be cleared by: manual work-arounds with technical answers, or
product notices; changes to the silicon (very rare); changes to the
software (so that the problem is worked around automatically; and
everything works as documented); or changes to the data sheet (so that the
issue is described properly).
The stepping system ensures "backward compatibility" which means that any
future chips MUST work with older bitstreams, in older designs. This means
that the customer does not have to worry that a new mask revision will
cause all of your previous IP to suddenly be "broken" and need to be
regenerated!
Some other manufacturers are on their n-th revision of silicon, and have
no "stepping" system at all, nor any policy about what they are doing (to
you).
If anything, I would require a properly documented stepping policy for
approval of any component, so that I would be sure that I would not be
"surprised" in any future shipment.
To this end, Virtex 4 was one of the first products to have the fully
implemented stepping system in place. Eventually all products will use
the system.
As always, if your company has its own policies, with their own
requirements, Xilinx is more than willing to work with you to establish
your own required flow to meet those needs. Some examples are customers
who require samples of the new stepping, and need 90 days before the new
stepping is allowed to be shipped to them as production. These
requirements are quite common with automotive suppliers, for example.
If you have any other concerns or questions on stepping, please consult
your Xilinx FAE. As well, if you have any questions or concerns about
errata, also consult your FAE.
Austin
Engine wrote:
A friend send me a document link.
http://direct.xilinx.com/bvdocs/notifications/xcn05025.pdf
He suggest we do not select Virtex4 in our projects.
I am not sure the real meaning of this document.
Does it mean that there are three bugs in the step 1 Virtex4 LX/SX?
Why do not call the Step 2 LX/SX as the mass production LX/SX?
Are there still bugs in step 2 LX/SX?
Whether step 3 LX/SX will be relased later?
Why FX is in step 0 now, what's the defination of step 0?
Please help me!
If it is ture, I would like to use the old VirtexII or Stratix on my
projects.
Thanks,
Engine
|
|
|
| Back to top |
|
|
Engine
Guest
|
| Posted:
Wed Dec 28, 2005 5:15 pm Post subject:
Re: Xilinx Stepping Methodology |
|
|
I see.
As the backward compatibility must be executed in silicon level, not
software level, I guess it will be a challenge job for your team.
:-)
Thank you very much!
Engine
Austin Lesea wrote,
| Quote: | Engine,
Well, we did not invent stepping, Intel did.
Stepping is just another way to keep track of what you are shipping.
Let me give you an example:
We go to production, even perhaps with errata:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14052
which is an example of an errata for Virtex 2 Pro.
Errata are items that are presently not working as they are described in
the documentation.
Errata can be cleared by: manual work-arounds with technical answers, or
product notices; changes to the silicon (very rare); changes to the
software (so that the problem is worked around automatically; and
everything works as documented); or changes to the data sheet (so that the
issue is described properly).
The stepping system ensures "backward compatibility" which means that any
future chips MUST work with older bitstreams, in older designs. This means
that the customer does not have to worry that a new mask revision will
cause all of your previous IP to suddenly be "broken" and need to be
regenerated!
Some other manufacturers are on their n-th revision of silicon, and have
no "stepping" system at all, nor any policy about what they are doing (to
you).
If anything, I would require a properly documented stepping policy for
approval of any component, so that I would be sure that I would not be
"surprised" in any future shipment.
To this end, Virtex 4 was one of the first products to have the fully
implemented stepping system in place. Eventually all products will use
the system.
As always, if your company has its own policies, with their own
requirements, Xilinx is more than willing to work with you to establish
your own required flow to meet those needs. Some examples are customers
who require samples of the new stepping, and need 90 days before the new
stepping is allowed to be shipped to them as production. These
requirements are quite common with automotive suppliers, for example.
If you have any other concerns or questions on stepping, please consult
your Xilinx FAE. As well, if you have any questions or concerns about
errata, also consult your FAE.
Austin
Engine wrote:
A friend send me a document link.
http://direct.xilinx.com/bvdocs/notifications/xcn05025.pdf
He suggest we do not select Virtex4 in our projects.
I am not sure the real meaning of this document.
Does it mean that there are three bugs in the step 1 Virtex4 LX/SX?
Why do not call the Step 2 LX/SX as the mass production LX/SX?
Are there still bugs in step 2 LX/SX?
Whether step 3 LX/SX will be relased later?
Why FX is in step 0 now, what's the defination of step 0?
Please help me!
If it is ture, I would like to use the old VirtexII or Stratix on my
projects.
Thanks,
Engine
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