Hello all,
I am new to this group, but it has already been a great resource..
thanks to all who post advice and suggestions! Good stuff.
My current issue involves the Virtex-4 configuration pin called CCLK,
which according to the V-4 Configuration Guide, "is different from
previous Xilinx FPGAs" and requires parallel Thevenin termination.
Basically, a 50 ohm resistor pulled up to Vcco/2, OR a 100 ohm pulled
up to Vcco and a 100 ohm pulled down to GND. Two questions:
1) Is this REALLY necessary, or just a good thing to have when
configuring a device at higher CCLK frequencies? What if I just clock
the bitstream at, say, 1 MHz?
2) What should I do since I want to have the option of using both
Master Serial and Slave Serial? The CCLK signal will potentially
terminate at either side, so where should the termination resistor(s)
be placed?
Thanks in advance,
-mike.
Virtex-4 CCLK termination
17 posts
• Page 1 of 2 • 1, 2
Re: Virtex-4 CCLK termination
by Austin Lesea » Wed Dec 28, 2005 1:15 am
Mike,
Frequency does not matter. It is all about rise time.
A fast rise time will create reflections. Reflections will create
multiple edges. Multiple edges will cause double clocking. Double
clocking will cause the device to be confused, and not configure.
If you simulate the entire trace for CCLK, with the actual dimensions,
and impedances, and loads and drivers (such as using Mentor's Hyperlynx
SI tool), you will see what I am referring to.
Also, if you simulate the run, you may find how to do this without a
termination.
It is so much simpler if we just tell you to do this as a best practice,
rather than require you to simulate the trace, and design the net such
that it has no reflections.
Typically CCLK runs to many devices, so making such a net have no
reflections is not possible without a parallel termination at the end of
the run.
Austin
shogmic wrote:
Frequency does not matter. It is all about rise time.
A fast rise time will create reflections. Reflections will create
multiple edges. Multiple edges will cause double clocking. Double
clocking will cause the device to be confused, and not configure.
If you simulate the entire trace for CCLK, with the actual dimensions,
and impedances, and loads and drivers (such as using Mentor's Hyperlynx
SI tool), you will see what I am referring to.
Also, if you simulate the run, you may find how to do this without a
termination.
It is so much simpler if we just tell you to do this as a best practice,
rather than require you to simulate the trace, and design the net such
that it has no reflections.
Typically CCLK runs to many devices, so making such a net have no
reflections is not possible without a parallel termination at the end of
the run.
Austin
shogmic wrote:
Hello all,
I am new to this group, but it has already been a great resource..
thanks to all who post advice and suggestions! Good stuff.
My current issue involves the Virtex-4 configuration pin called CCLK,
which according to the V-4 Configuration Guide, "is different from
previous Xilinx FPGAs" and requires parallel Thevenin termination.
Basically, a 50 ohm resistor pulled up to Vcco/2, OR a 100 ohm pulled
up to Vcco and a 100 ohm pulled down to GND. Two questions:
1) Is this REALLY necessary, or just a good thing to have when
configuring a device at higher CCLK frequencies? What if I just clock
the bitstream at, say, 1 MHz?
2) What should I do since I want to have the option of using both
Master Serial and Slave Serial? The CCLK signal will potentially
terminate at either side, so where should the termination resistor(s)
be placed?
Thanks in advance,
-mike.
- Austin Lesea
Re: Virtex-4 CCLK termination
by Brad Smallridge » Wed Dec 28, 2005 8:05 am
I would suggest doing whatever they say. I have had trouble designing a
Spartan board downloading at 5Mhz. Adding the resistors helped quite a bit
but still I have some flyby taps at about 10mm that still give me trouble.
It also helps if you can turn off the other clocks during your download
periods.
Don't know about your master/slave problem. Perhaps you can add a series
resistance and get by with that as, as you say, you want to clock at 1 MHz.
"shogmic" <shogmic@iit.edu> wrote in message
news:1135721828.251908.18690@g47g2000cwa.googlegroups.com...
Spartan board downloading at 5Mhz. Adding the resistors helped quite a bit
but still I have some flyby taps at about 10mm that still give me trouble.
It also helps if you can turn off the other clocks during your download
periods.
Don't know about your master/slave problem. Perhaps you can add a series
resistance and get by with that as, as you say, you want to clock at 1 MHz.
"shogmic" <shogmic@iit.edu> wrote in message
news:1135721828.251908.18690@g47g2000cwa.googlegroups.com...
Hello all,
I am new to this group, but it has already been a great resource..
thanks to all who post advice and suggestions! Good stuff.
My current issue involves the Virtex-4 configuration pin called CCLK,
which according to the V-4 Configuration Guide, "is different from
previous Xilinx FPGAs" and requires parallel Thevenin termination.
Basically, a 50 ohm resistor pulled up to Vcco/2, OR a 100 ohm pulled
up to Vcco and a 100 ohm pulled down to GND. Two questions:
1) Is this REALLY necessary, or just a good thing to have when
configuring a device at higher CCLK frequencies? What if I just clock
the bitstream at, say, 1 MHz?
2) What should I do since I want to have the option of using both
Master Serial and Slave Serial? The CCLK signal will potentially
terminate at either side, so where should the termination resistor(s)
be placed?
Thanks in advance,
-mike.
- Brad Smallridge
Re: Virtex-4 CCLK termination
by Peter Alfke » Wed Dec 28, 2005 9:15 am
Bob wrote:
destination. Just put a series-terminating resistor right at the
driver, and let the isgnal bounce up to full amplitude at the openended
destination. But never (never!) use source termination when you are
drving multiple detinations along a clock trace. The half-amplitude
signal travelling along the line will cause you lots of grief.
Peter Alfke
We did a board that had a "double-pulse" problem on a 1MHz JTAG test port
(one TCK buffer output driving multiple JTAG ports). Now, we distribute TCK
like any other clock, and source terminate each buffer output.
Source termination is great if you have one source driving a single
destination. Just put a series-terminating resistor right at the
driver, and let the isgnal bounce up to full amplitude at the openended
destination. But never (never!) use source termination when you are
drving multiple detinations along a clock trace. The half-amplitude
signal travelling along the line will cause you lots of grief.
Peter Alfke
- Peter Alfke
Re: Virtex-4 CCLK termination
by Peter Alfke » Wed Dec 28, 2005 9:15 am
Bob wrote:
destination. Just put a series-terminating resistor right at the
driver, and let the isgnal bounce up to full amplitude at the openended
destination. But never (never!) use source termination when you are
drving multiple detinations along a clock trace. The half-amplitude
signal travelling along the line will cause you lots of grief.
Peter Alfke
We did a board that had a "double-pulse" problem on a 1MHz JTAG test port
(one TCK buffer output driving multiple JTAG ports). Now, we distribute TCK
like any other clock, and source terminate each buffer output.
Source termination is great if you have one source driving a single
destination. Just put a series-terminating resistor right at the
driver, and let the isgnal bounce up to full amplitude at the openended
destination. But never (never!) use source termination when you are
drving multiple detinations along a clock trace. The half-amplitude
signal travelling along the line will cause you lots of grief.
Peter Alfke
- Peter Alfke
Re: Virtex-4 CCLK termination
by Peter Alfke » Wed Dec 28, 2005 9:15 am
Bob wrote:
Perhaps effective, but really just camouflaging the true problem.
The true problem is improper lay-out or wrong termination, generating
double-pulses from the fast transitions. The CCLK frequency itself is
irrelevant.
Peter Alfke
I guess it's safe for me to come out-of-the-closet, now. Thanks for your
honesty, Peter.
My suggestion is like a band-aid or an aspirin.
Perhaps effective, but really just camouflaging the true problem.
The true problem is improper lay-out or wrong termination, generating
double-pulses from the fast transitions. The CCLK frequency itself is
irrelevant.
Peter Alfke
- Peter Alfke
Re: Virtex-4 CCLK termination
by Bob » Wed Dec 28, 2005 9:15 am
"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1135743326.126840.299580@g47g2000cwa.googlegroups.com...
Yep, that's a common misconception that it's the frequency that causes
reflections.
We did a board that had a "double-pulse" problem on a 1MHz JTAG test port
(one TCK buffer output driving multiple JTAG ports). Now, we distribute TCK
like any other clock, and source terminate each buffer output.
It all seems so easy, now, but it's taken a couple of 'ahshits' to get
there.
Bob
news:1135743326.126840.299580@g47g2000cwa.googlegroups.com...
Bob wrote:
I guess it's safe for me to come out-of-the-closet, now. Thanks for your
honesty, Peter.
My suggestion is like a band-aid or an aspirin.
Perhaps effective, but really just camouflaging the true problem.
The true problem is improper lay-out or wrong termination, generating
double-pulses from the fast transitions. The CCLK frequency itself is
irrelevant.
Peter Alfke
Yep, that's a common misconception that it's the frequency that causes
reflections.
We did a board that had a "double-pulse" problem on a 1MHz JTAG test port
(one TCK buffer output driving multiple JTAG ports). Now, we distribute TCK
like any other clock, and source terminate each buffer output.
It all seems so easy, now, but it's taken a couple of 'ahshits' to get
there.
Bob
- Bob
Re: Virtex-4 CCLK termination
by Bob » Wed Dec 28, 2005 9:15 am
"Peter Alfke" <alfke@sbcglobal.net> wrote in message
Wow, I'm so relieved to see that someone else has done this. The real trick,
however, is to make sure that this hack works long enough, in production, so
that your stock options are vested, exercised, and sold.
I guess it's safe for me to come out-of-the-closet, now. Thanks for your
honesty, Peter.
Bob
If everything else fails, you can load the clock with 100 pF, but that
is just a dirty emergency repair.
Wow, I'm so relieved to see that someone else has done this. The real trick,
however, is to make sure that this hack works long enough, in production, so
that your stock options are vested, exercised, and sold.
I guess it's safe for me to come out-of-the-closet, now. Thanks for your
honesty, Peter.
Bob
- Bob
Re: Virtex-4 CCLK termination
by Peter Alfke » Wed Dec 28, 2005 9:15 am
As Austin wrote, the frequency does not matter, the rise/fll time does,
and it is really not under your control.
So, make sure that the CCLK distribution is one serial "worm". not a
tree with many branches. then terminate it at the very end. Your enemy
are the reflections that result in double-triggering.
If everything else fails, you can load the clock with 100 pF, but that
is just a dirty emergency repair. Another dirty trick is to put 10 Ohm
in series with the CCLK driver, and then decouple the downstream side
of that resistor with 100 pF. Austin would never recommend this, but I
sense your desperation...
Peter Alfke
shogmic wrote:
and it is really not under your control.
So, make sure that the CCLK distribution is one serial "worm". not a
tree with many branches. then terminate it at the very end. Your enemy
are the reflections that result in double-triggering.
If everything else fails, you can load the clock with 100 pF, but that
is just a dirty emergency repair. Another dirty trick is to put 10 Ohm
in series with the CCLK driver, and then decouple the downstream side
of that resistor with 100 pF. Austin would never recommend this, but I
sense your desperation...
Peter Alfke
shogmic wrote:
Hello all,
I am new to this group, but it has already been a great resource..
thanks to all who post advice and suggestions! Good stuff.
My current issue involves the Virtex-4 configuration pin called CCLK,
which according to the V-4 Configuration Guide, "is different from
previous Xilinx FPGAs" and requires parallel Thevenin termination.
Basically, a 50 ohm resistor pulled up to Vcco/2, OR a 100 ohm pulled
up to Vcco and a 100 ohm pulled down to GND. Two questions:
1) Is this REALLY necessary, or just a good thing to have when
configuring a device at higher CCLK frequencies? What if I just clock
the bitstream at, say, 1 MHz?
2) What should I do since I want to have the option of using both
Master Serial and Slave Serial? The CCLK signal will potentially
terminate at either side, so where should the termination resistor(s)
be placed?
Thanks in advance,
-mike.
- Peter Alfke
Re: Virtex-4 CCLK termination
by Bob » Wed Dec 28, 2005 5:15 pm
Symon,
The most recent 'ahshit' was the problem regarding a daisy-chained JTAG TCK
line. This definitely would have shown up in simulation, but who would think
to simulate a stinking JTAG port? Now, it's the only thing I think about :-)
You're correct. Buffering, in itself, may cause a worse problem. However, if
you buffer each clock input separately (so you only have point-to-point
connections per clock drive/input pair) and add a source termination
resistor, close to each buffer's output pin, then you shouldn't have any
clock edge SI problems. This is what we do, now, for JTAG TCK's and FPGA
CCLK's.
We have grown to depend on HyperLynx, and most recently SiSoft. When in
doubt -- simulate. When confident -- still simulate!
Bob
"Symon" <symon_brewer@hotmail.com> wrote in message
news:43b27fd0$0$15785$14726298@news.sunsite.dk...
The most recent 'ahshit' was the problem regarding a daisy-chained JTAG TCK
line. This definitely would have shown up in simulation, but who would think
to simulate a stinking JTAG port? Now, it's the only thing I think about :-)
You're correct. Buffering, in itself, may cause a worse problem. However, if
you buffer each clock input separately (so you only have point-to-point
connections per clock drive/input pair) and add a source termination
resistor, close to each buffer's output pin, then you shouldn't have any
clock edge SI problems. This is what we do, now, for JTAG TCK's and FPGA
CCLK's.
We have grown to depend on HyperLynx, and most recently SiSoft. When in
doubt -- simulate. When confident -- still simulate!
Bob
"Symon" <symon_brewer@hotmail.com> wrote in message
news:43b27fd0$0$15785$14726298@news.sunsite.dk...
Hi Bob,
The answer is to do as Austin says and simulate the thing. No 'ahshits' or
bodged on caps needed. The Mentor marketing hype is pretty close when it
says that the tool pays for itself in just 1 or 2 PCB respins because the
SI is bad first time.
It also makes sure that your design isn't marginal. Two 'ahshits' may have
got your design working, but will it survive the next rev. of the silicon
because it only just worked?
BTW, another misconception is that buffering always fixes the problem.
Most buffers are very good at driving lines with faster rise times than
the original driver. This makes the problem even worse.
Best, Syms.
p.s. I chuckled at Brad's "I would suggest doing whatever they (Xilinx)
say."! I'd suggest maybe using their designs as a start, then think about
your own application. Remember, Xilinx has to suggest things that will
work for a multitude of designs. This may not be the most efficient for
your design. In fact I'd question whether a 'one size fits all' is even
possible at all for some situations.
"Bob" <nimby1_notspamm_@earthlink.net> wrote in message
news:7Bpsf.3534$R84.1704@newsread2.news.pas.earthlink.net...
Yep, that's a common misconception that it's the frequency that causes
reflections.
We did a board that had a "double-pulse" problem on a 1MHz JTAG test port
(one TCK buffer output driving multiple JTAG ports). Now, we distribute
TCK like any other clock, and source terminate each buffer output.
It all seems so easy, now, but it's taken a couple of 'ahshits' to get
there.
- Bob
Re: Virtex-4 CCLK termination
by Symon » Wed Dec 28, 2005 5:15 pm
Hi Bob,
The answer is to do as Austin says and simulate the thing. No 'ahshits' or
bodged on caps needed. The Mentor marketing hype is pretty close when it
says that the tool pays for itself in just 1 or 2 PCB respins because the SI
is bad first time.
It also makes sure that your design isn't marginal. Two 'ahshits' may have
got your design working, but will it survive the next rev. of the silicon
because it only just worked?
BTW, another misconception is that buffering always fixes the problem. Most
buffers are very good at driving lines with faster rise times than the
original driver. This makes the problem even worse.
Best, Syms.
p.s. I chuckled at Brad's "I would suggest doing whatever they (Xilinx)
say."! I'd suggest maybe using their designs as a start, then think about
your own application. Remember, Xilinx has to suggest things that will work
for a multitude of designs. This may not be the most efficient for your
design. In fact I'd question whether a 'one size fits all' is even possible
at all for some situations.
"Bob" <nimby1_notspamm_@earthlink.net> wrote in message
news:7Bpsf.3534$R84.1704@newsread2.news.pas.earthlink.net...
The answer is to do as Austin says and simulate the thing. No 'ahshits' or
bodged on caps needed. The Mentor marketing hype is pretty close when it
says that the tool pays for itself in just 1 or 2 PCB respins because the SI
is bad first time.
It also makes sure that your design isn't marginal. Two 'ahshits' may have
got your design working, but will it survive the next rev. of the silicon
because it only just worked?
BTW, another misconception is that buffering always fixes the problem. Most
buffers are very good at driving lines with faster rise times than the
original driver. This makes the problem even worse.
Best, Syms.
p.s. I chuckled at Brad's "I would suggest doing whatever they (Xilinx)
say."! I'd suggest maybe using their designs as a start, then think about
your own application. Remember, Xilinx has to suggest things that will work
for a multitude of designs. This may not be the most efficient for your
design. In fact I'd question whether a 'one size fits all' is even possible
at all for some situations.
"Bob" <nimby1_notspamm_@earthlink.net> wrote in message
news:7Bpsf.3534$R84.1704@newsread2.news.pas.earthlink.net...
Yep, that's a common misconception that it's the frequency that causes
reflections.
We did a board that had a "double-pulse" problem on a 1MHz JTAG test port
(one TCK buffer output driving multiple JTAG ports). Now, we distribute
TCK like any other clock, and source terminate each buffer output.
It all seems so easy, now, but it's taken a couple of 'ahshits' to get
there.
- Symon
Re: Virtex-4 CCLK termination
by Bevan Weiss » Thu Dec 29, 2005 1:15 am
Thanks a lot for your posts... Frequency does not matter - I did not
know that. Thanks for the lesson.
Well it is the frequency that's important, it's just not the fundamental
frequency so much as the harmonics.
With decreasing rise and fall times the amplitudes of the harmonics
become more pronounced, and there are more of them which contribute to
the overall waveshape. This means that any distortion of these
harmonics will result in a much degraded waveshape.
This is why termination effects are more important as the fundamental
frequency increases, because the harmonics are situated at higher
frequencies also and more likely to be interfered with by the impedance
mismatches.
Still no easy answer to the Master or Slave configuration flexibility,
but maybe I will just have to choose one or the other right now in
order to terminate CCLK properly. I may also throw on the parallel
termination on both ends and only populate one set, depending on which
configuration mode I choose.
If you're only driving the line from one end then you could add parallel
terminations at each receiving node (to bring the total impedance seen
by the driver to it's nominal impedance). For a 50Ohm driver and
infinite impedance receiving nodes the parallel impedances should be
70.7Ohms I believe.
If several nodes may drive the line then you might get away with simply
adding a combination of parallel and series terminations.
- Bevan Weiss
Re: Virtex-4 CCLK termination
by Austin Lesea » Thu Dec 29, 2005 1:15 am
Right,
One termination, only at the end of the line. Can not do both (maybe
you could, but you would have to simulate the driver to see if it is
strong enough).
I like your idea of being able to select the end you want terminated.
Either just place the resistors at the 'end' that is really the end (of
the line), or solder them at the 'beginning' if that turns out to really
be the end (of the line).
Austin
shogmic wrote:
One termination, only at the end of the line. Can not do both (maybe
you could, but you would have to simulate the driver to see if it is
strong enough).
I like your idea of being able to select the end you want terminated.
Either just place the resistors at the 'end' that is really the end (of
the line), or solder them at the 'beginning' if that turns out to really
be the end (of the line).
Austin
shogmic wrote:
Peter Alfke wrote:
Source termination is great if you have one source driving a single
destination. Just put a series-terminating resistor right at the
driver, and let the isgnal bounce up to full amplitude at the openended
destination. But never (never!) use source termination when you are
drving multiple detinations along a clock trace. The half-amplitude
signal travelling along the line will cause you lots of grief.
Peter Alfke
Hey guys,
Thanks a lot for your posts... Frequency does not matter - I did not
know that. Thanks for the lesson.
Still no easy answer to the Master or Slave configuration flexibility,
but maybe I will just have to choose one or the other right now in
order to terminate CCLK properly. I may also throw on the parallel
termination on both ends and only populate one set, depending on which
configuration mode I choose.
It is only 1 Virtex-4 SX FPGA being configured, but I will have a PROM
and another FPGA (Spartan-III) attached to the CCLK line. Most likely,
the Spartan or the PROM will drive the CCLK, but I definitely do want
the ability for either one to drive it. Sounds like parallel
termination, then, near the Virtex-4 would be my best bet.. I assume
that source termination at both the PROM and the Spartan is out of the
question since one will act like an additional destination when the
other is driving CCLK?
Thanks,
mike.
- Austin Lesea
Re: Virtex-4 CCLK termination
by shogmic » Thu Dec 29, 2005 1:15 am
Peter Alfke wrote:
Hey guys,
Thanks a lot for your posts... Frequency does not matter - I did not
know that. Thanks for the lesson.
Still no easy answer to the Master or Slave configuration flexibility,
but maybe I will just have to choose one or the other right now in
order to terminate CCLK properly. I may also throw on the parallel
termination on both ends and only populate one set, depending on which
configuration mode I choose.
It is only 1 Virtex-4 SX FPGA being configured, but I will have a PROM
and another FPGA (Spartan-III) attached to the CCLK line. Most likely,
the Spartan or the PROM will drive the CCLK, but I definitely do want
the ability for either one to drive it. Sounds like parallel
termination, then, near the Virtex-4 would be my best bet.. I assume
that source termination at both the PROM and the Spartan is out of the
question since one will act like an additional destination when the
other is driving CCLK?
Thanks,
mike.
Source termination is great if you have one source driving a single
destination. Just put a series-terminating resistor right at the
driver, and let the isgnal bounce up to full amplitude at the openended
destination. But never (never!) use source termination when you are
drving multiple detinations along a clock trace. The half-amplitude
signal travelling along the line will cause you lots of grief.
Peter Alfke
Hey guys,
Thanks a lot for your posts... Frequency does not matter - I did not
know that. Thanks for the lesson.
Still no easy answer to the Master or Slave configuration flexibility,
but maybe I will just have to choose one or the other right now in
order to terminate CCLK properly. I may also throw on the parallel
termination on both ends and only populate one set, depending on which
configuration mode I choose.
It is only 1 Virtex-4 SX FPGA being configured, but I will have a PROM
and another FPGA (Spartan-III) attached to the CCLK line. Most likely,
the Spartan or the PROM will drive the CCLK, but I definitely do want
the ability for either one to drive it. Sounds like parallel
termination, then, near the Virtex-4 would be my best bet.. I assume
that source termination at both the PROM and the Spartan is out of the
question since one will act like an additional destination when the
other is driving CCLK?
Thanks,
mike.
- shogmic
Re: Virtex-4 CCLK termination
by Peter Alfke » Thu Dec 29, 2005 9:10 am
Bevan Weiss wrote:
Bevan, your description is not totally wrong, but it is misleading.
Obviously, any given repetitive event can be correctly described either
in the time domain or in the frequency domain. You prefer the frequency
domain, bur I say that the time domain is more meaningful in this case.
The user has control over the repetition rate (the fundamental
frequency) but not over the rise and fall times. And these two
phenomena are really not ineterrelated. If you change the fundamental
frequency, the rise and fall times do not change, and neither does the
damage caused by these rise and fall times. It is thus misleading to
describe them as harmonics (although technically they are). If you
change the fundamental frequency by an order of magnitude, the problems
caused by the sharp transition times do not change at all. That's why
we say: The problem is the transition time, not the fundamental
frequency.
Peter Alfke
Well it is the frequency that's important, it's just not the fundamental
frequency so much as the harmonics.
With decreasing rise and fall times the amplitudes of the harmonics
become more pronounced, and there are more of them which contribute to
the overall waveshape. This means that any distortion of these
harmonics will result in a much degraded waveshape.
This is why termination effects are more important as the fundamental
frequency increases, because the harmonics are situated at higher
frequencies also and more likely to be interfered with by the impedance
mismatches.
Bevan, your description is not totally wrong, but it is misleading.
Obviously, any given repetitive event can be correctly described either
in the time domain or in the frequency domain. You prefer the frequency
domain, bur I say that the time domain is more meaningful in this case.
The user has control over the repetition rate (the fundamental
frequency) but not over the rise and fall times. And these two
phenomena are really not ineterrelated. If you change the fundamental
frequency, the rise and fall times do not change, and neither does the
damage caused by these rise and fall times. It is thus misleading to
describe them as harmonics (although technically they are). If you
change the fundamental frequency by an order of magnitude, the problems
caused by the sharp transition times do not change at all. That's why
we say: The problem is the transition time, not the fundamental
frequency.
Peter Alfke
- Peter Alfke
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