Symon
Guest
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 Posted:
Thu Dec 29, 2005 4:02 pm Post subject:
Re: Virtex-4 CCLK termination |
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"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1135825838.800221.321020@g47g2000cwa.googlegroups.com...
| Quote: | If you change the fundamental
frequency, the rise and fall times do not change, and neither does the
damage caused by these rise and fall times.
Hi Peter, |
Here's a time-domain counter-example to your premise.
A fast rising edge arrives at a badly terminated node. The signals reflect
back and forth causing (say) a ringing effect. Luckily, the amplitude of
this ringing is not enough to change the state of the receiver input, so all
works well. After a while the ringing dies down. After the ringing has died
down the falling edge arrives and there's no problem.
OK, now the same thing but with a faster fundamental:-
A fast rising edge arrives at a badly terminated node. The signals reflect
back and forth causing (say) a ringing effect. Luckily, the amplitude of
this ringing is not enough to change the state of the receiver, so all works
well, until the falling edge arrives while the line is still ringing. The
combination of the falling edge and the ringing causes the receiver to see a
rising edge. Not good.
In this case, the fundamental frequency DOES affect the circuit.
On a separate point, it's as well to remember that digital ICs inputs aren't
a simple hi-impedance open circuit. They have some amount of capacitance.
(See Symon vs. Austin vs. Brian in CAF passim!) This means that low
frequencies see the input as an open, but very high frequencies see them as
a short. For a Xilinx FPGA, the 50 ohm impedance point is at about 300MHz.
Ish. I do know at least one bloke whose brain apparently has a hard-wired
Smith chart in it. Mine doesn't have this feature so I simulate, or, if
we're down the pub, ask my mate!
Cheers, Syms. |
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Austin Lesea
Guest
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| Posted:
Thu Dec 29, 2005 5:15 pm Post subject:
Re: Virtex-4 CCLK termination |
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Symon,
I also prefer to look at it as rise and fall times causing problems.
Obviously, anything that happens in the time domain is also happening in
the frequency domain, and the opposite as well. We are just observers
trying to understand what happened. The clock pulse itself exists in
both domains simultaneously.
It is like the physics student who asked the professor "is light a
particle or a wave?" The answer, of course, is 'yes.' Sometimes
modeling it as a particle gives you insight into what happened, and
sometimes modeling it as a wave tells you something useful.
So it is with reflections. If the rising edge gets a kink in it due to
a reflection, it is easier to explain it as fast rising edges hitting a
discontinuity and reflecting in the time domain. Is it 'wrong' to say
that the clock frequency is the cause of the problem (even though we
both know that frequency and time are two ways of describing the physics
of the system)? I think so, the frequency model is the wrong approach
to understand what is happening (to a pulse on a wire).
If I am trying to explain a clock pulse on a wire, I think the time
domain is the best choice.
Austin
Symon wrote:
| Quote: | "Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1135825838.800221.321020@g47g2000cwa.googlegroups.com...
If you change the fundamental
frequency, the rise and fall times do not change, and neither does the
damage caused by these rise and fall times.
Hi Peter,
Here's a time-domain counter-example to your premise.
A fast rising edge arrives at a badly terminated node. The signals reflect
back and forth causing (say) a ringing effect. Luckily, the amplitude of
this ringing is not enough to change the state of the receiver input, so all
works well. After a while the ringing dies down. After the ringing has died
down the falling edge arrives and there's no problem.
OK, now the same thing but with a faster fundamental:-
A fast rising edge arrives at a badly terminated node. The signals reflect
back and forth causing (say) a ringing effect. Luckily, the amplitude of
this ringing is not enough to change the state of the receiver, so all works
well, until the falling edge arrives while the line is still ringing. The
combination of the falling edge and the ringing causes the receiver to see a
rising edge. Not good.
In this case, the fundamental frequency DOES affect the circuit.
On a separate point, it's as well to remember that digital ICs inputs aren't
a simple hi-impedance open circuit. They have some amount of capacitance.
(See Symon vs. Austin vs. Brian in CAF passim!) This means that low
frequencies see the input as an open, but very high frequencies see them as
a short. For a Xilinx FPGA, the 50 ohm impedance point is at about 300MHz.
Ish. I do know at least one bloke whose brain apparently has a hard-wired
Smith chart in it. Mine doesn't have this feature so I simulate, or, if
we're down the pub, ask my mate!
Cheers, Syms.
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