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motty · Guest

Hey all,

I am trying to play around with Synplify and an EDK project I have
already implemented solely in the EDK. I have flagged the "IMP_NETLIST
= FALSE" in all the user IP in the project. Then I use the "Export to
ProjNav" in the Tools menu.

Opening the resulting "system.ise" project in the ISE tool works
correctly. All the core vhdl and verilog "wrapper" files are added as
sources correctly, but since the EDK did not synthesize the user IP,
they all show up as "?" sources in the project.

So just messing around, I pulled in the top level vhdl for one of my
IP. This is the vhdl file that the import peripheral wizard made, and
the one that I filled in correctly. Again, this project works fine in
the EDK, so all files for all IP's are correct.

Once I add that top vhdl file as a source, and the associated files for
my IP, everything looks OK except for the opb_ipif source referenced in
the vhdl file. It shows up as a "?" source. OK, so I add the source
from the common libraries. So the opb_ipif looks OK, but it references
sources that reference sources that reference sources, etc, etc, etc.
I started adding all the sources it asked for. But then it gets down
to some that are not even on the hard drive of my machine. They are
nowhere to be found. So of course, the Synplicity errors out.

Is there a way to do what I am trying to do? Basically, I want the EDK
to synthesize the Xilinx IP and Synplicity to synthesize the user IP
via the ISE. Then I guess I would pull the finalized bitstream back
into the EDK for final compilation and download.

I know I could probably black-box the user IP in the ISE first and then
pull that into the EDK. But I am just messing around, evaluating what
can and cannot be done using Synpilcity. It is a VERY expensive tool
that we are trying to see is worth justifying.

Thanks,

Tom

Mike Treseler · Guest

motty wrote:

motty · Guest

Hey Bob,

I have looked at that document. It tells how to use the EDK to
generate the embedded system and then import that into Synplify. This
INCLUDES the user IP from the system. Then it explains how you can add
other logic around the processor subsystem. But the user IP is STILL
synthesized using XST.

I do not want to use XST except for the Xilinx IP synthesis. I am
trying a couple of different things, but haven't had any luck yet.

Thanks though,

Tom

Bob Efram · Guest

Hi,

There is an appnote on Synplicity's Website
that may help:

http://www.synplicity.com/literature/pdf/Using_Synplify_with_EDK.pdf

Happy New Year,

Bob

Synplicity FAE - Colorado.

motty · Guest

OK, I lied! The article does mention using Synplify to synthesize user
IP, but it also says a future article will be available specifically
addressing that issue. I guess I would like to see that article.

It seems that the app note hints that a user IP can be synthesized from
the user_logic level down, black-box imported into the project, wrapped
and instantiated in the IP_name.vhd file, and then synthesized using
XST in the end. So the user_logic is as far up the module as you can
go. I would agree with that. Trying to synthesize the IP_name.vhd
file results in having to reference a TON of other files associated
with the opb_bus IP. And I never got that to work anyways.

Also, it could work to change to a custom make file for the synthesis,
point to different scipts for each IP, and then use Synplify that way,
but that seems like a lot of work.

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