logjam
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 Posted:
Fri Dec 30, 2005 1:15 am Post subject:
Brute Force Examination of a PLD |
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Lets discuss the brute force examination of a PAL16R8, for example,
with absolutely no knowledge of its function.
Lets assume a 16R8.
Could we just clear all the inputs and toggle the clock line a few
times and wait for a known output (that is, if there are any of the
clocked feedback signals used, get them to the same state) and then on
the next clock state try a new input?
So...
Refresh the PAL to a known state, try value $01, try $01
Refresh the PAL to a known state, try value $01, try $02
Refresh the PAL to a known state, try value $01, try $03
Until we get a truth table with 65,535 results.
Can anyone help me think of a situation where this would NOT work?
I suppose the next "problem" would be reducing and deciphering the
equation.
Lets assume there are no GALs being tested, only a 16R8. |
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