Presto
Joined: 24 Oct 2005
Posts: 1
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 Posted:
Mon Jan 16, 2006 4:57 pm Post subject:
Any experience with MCH_OPB_DDR? |
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I'm trying to use this core in the EDK 7.1 for a shared memory application. The processor is supposed to access the DDR DRAM through OPB interface, and another high speed peripheral accesses the DRAM through an FSL like channel.
However, I got problems with it. I've tried several configurations. None of them provides successful access through the OPB bus, i.e. memory test fails all the time. Actually, only the last two 32bit words left in the memory. For example, if I fill it up with 0xAA5500FF, then the test is passed. However, if I wirte serial numbers, like 0x00000001, 0x00000002, ... 0x10000000, 0x10000012, then when I read the first two memory words, I get 0x10000000, 0x10000012 instead of 0x00000001, 0x00000002.
FYI, I'm using XUP V2P board with 512MB DDR DIMM memory.
Has anyone used this core before? Many thanks. |
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