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opikalo1
Joined: 26 May 2006
Posts: 3
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 Posted:
Fri May 26, 2006 3:53 pm Post subject:
Xilinx ML403 board with GSRD design - generating ACE files |
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Hello,
I have difficulty using SystemACE on ML403 with GSRD design and stand-alone application xlltemac_tx_rx.elf. The application would not start after uploading. It seems like the elf file is missing, but the bit file is uploaded correctly. I can manually upload executable elf file through xmd, and it will work.
I have EDK 7.1.02i / ISE 7.1.04
Any help?
Thanks,
Oleksiy |
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Bas
Joined: 13 Sep 2006
Posts: 2
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Thu Sep 14, 2006 6:55 am Post subject:
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Hi,
I use xmd to generate an ACE file out of a .bit and an .elf file. Then i use the compact flash card to store the ACE file and boot from.
| Code: | | xmd -jprog -board ml403 -hw implementation/system.bit -elf <elf location> -ace <ACE target location> -tcl <EDK install dir>data/xmd/genace.tcl |
Make sure to have set the correct PATH environment variables, in my case the path to powerpc-eabi-objcopy was unknown.
I have no experience uploading the ACE file directly, but if i encounter this, i'll let you know.
Bas |
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opikalo1
Joined: 26 May 2006
Posts: 3
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| Posted:
Thu Sep 14, 2006 2:12 pm Post subject:
Fix uploading bits and elf on ML403 |
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This question was answered by Xilinx representative. There should be a time delay between uploading bit file and uploading elf file. This is done by modyfing default genace.tcl script:
| Code: | # Production ML403
set ml403(xmd_options) "-configdevice devicenr 1 idcode 0x05059093 irlength 16 partname xcf32p -configdevice devicenr 2 idcode 0x01E58093 irlength 10 partname xc4vfx12 -configdevice devicenr 3 idcode 0x09608093 irlength 8 partname xc95144xl -debugdevice devicenr 2 cpunr 1 isocmStartAdr 0xffffc000 isocmSize 16384 isocmDcrStartAdr 0x100 dcrStartAdr 0x78008000 icacheStartAdr 0x10000000 itagStartAdr 0x10010000 dcacheStartAdr 0x10020000 dtagStartAdr 0x10030000 tlbStartAdr 0x10050000"
set ml403(jtag_fpga_position) 2
set ml403(jtag_devices) "xcf32p xc4vfx12 xc95144xl"
....
proc xmd_elf2svf { target_type elffile xmd_options } {
set svffile "[file rootname $elffile].svf"
puts "\n############################################################"
puts "Converting ELF file '$elffile' to SVF file '$svffile'"
set tgt 0
if { $target_type == "ppc_hw" } {
set a "xconnect ppc hw -cable type xilinx_svffile fname $svffile $xmd_options"
} else {
set a "xconnect mb mdm -cable type xilinx_svffile fname $svffile $xmd_options"
}
# puts "$a\n"
if { [catch {set tgt [eval $a]} retval] } {
puts "$retval"
error "ERROR: Unable to create SVF file '$svffile' for ELF file : $elffile"
}
#puts "xconnect Done..\n\n"
xreset $tgt
#add artificial delay here
set i 1
while { $i < 1000 } {
xrreg $tgt
incr i
}
xdownload $tgt $elffile
#puts "xdownload Done.. \n\n"
# Fix for PowerPC CPU errata 212/213 on Virtex4. Causes erroneous data to be loaded when data
# cache is loaded. Workaround is to set 1 and 3 bits of CCR0
if { $target_type == "ppc_hw" } {
xwreg $tgt 68 0x50700000
}
xdisconnect $tgt
#puts "xdisconnect Done..\n\n"
return
}
#no reset
proc xmd_data2svf { target_type dfile load_addr xmd_options } {
set svffile "[file rootname $dfile].svf"
puts "\n############################################################"
puts "Converting Data file '$dfile' to SVF file '$svffile'"
set tgt 0
if { $target_type == "ppc_hw" } {
set a "xconnect ppc hw -cable type xilinx_svffile fname $svffile $xmd_options"
} else {
set a "xconnect mb mdm -cable type xilinx_svffile fname $svffile $xmd_options"
}
# puts "$a\n"
if { [catch {set tgt [eval $a]} retval] } {
puts "$retval"
error "ERROR: Unable to create SVF file '$svffile' for Data file : $dfile"
}
#puts "xconnect Done..\n\n"
#xreset $tgt
xdownload $tgt -data $dfile $load_addr
#puts "xdownload Done.. \n\n"
xdisconnect $tgt
#puts "xdisconnect Done..\n\n"
return
}
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