fguihot
Joined: 11 Jul 2006
Posts: 2
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 Posted:
Tue Jul 11, 2006 7:53 am Post subject:
Help !!! synthesis problem under quartus 2 |
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Hello everybody.
I'm a user of cpld, and I was used to program under max2plus, in AHDL.
I migrated to quartus, but I encountered several problems.
I tried a very simple program. I want to build a delay line of serial expander.
In AHDL, we could define the serial expander, but quartus make logic simplification and doesn't provide the mean to counter these simplification. I asked the support, who told me to migrate to verilog/VHDL.
I follow their advice, but unfortunately, we could define serial expander in verilog/VHDL. It is implemented as a not gate. From the logic point of view, it is equivalent. From the timing point of view, it is totally different.
Does anyone know how to define an expander ??? Or do I have to go back to max2plus ??? |
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