| Author |
Message |
Moti
Guest
|
 Posted:
Mon Dec 06, 2004 7:02 pm Post subject:
Re: how to speed up my accumulator ?? |
|
|
Another question regarding the NCO...
Does any of you guys knows the algorithm for calculating the jitter
frequency on the NCO output (MSbit) .
I know that the jitter magnitude is + - [reference clock period / 2]
and I know that I can see it (the frequency) also in a Spectrum
analyzer but I will be glad to have a formula for calculating it in
advance.
Thanks again, Moti. |
|
| Back to top |
|
 |
John_H
Guest
|
| Posted:
Mon Dec 06, 2004 9:28 pm Post subject:
Re: how to speed up my accumulator ?? |
|
|
"Moti" <moti@terasync.net> wrote in message
news:1102341075.941696.112870@c13g2000cwb.googlegroups.com...
| Quote: | Another question regarding the NCO...
Does any of you guys knows the algorithm for calculating the jitter
frequency on the NCO output (MSbit) .
I know that the jitter magnitude is + - [reference clock period / 2]
and I know that I can see it (the frequency) also in a Spectrum
analyzer but I will be glad to have a formula for calculating it in
advance.
Thanks again, Moti.
|
It's a bit involved to find the largest jitter components but I've worked
the problem in the past and found a direct correlation between my expected
jitter components and the FFT of the NCO output. Effectively, your jitter
components are at the offsets between the frequency of your NCO and the best
fractions that approximate your NCO output-to-input frequency ratio (and the
harmonics thereof). If you can figure the closest fractions in sequency,
you can get your main jitter components. There is some mixing among these
frequencies but it tends to be significantly lower than the main peaks in
the scenarios I ran. |
|
| Back to top |
|
|
Moti
Guest
|
| Posted:
Mon Dec 06, 2004 10:20 pm Post subject:
Re: how to speed up my accumulator ?? |
|
|
Hi Jhon,
thanks for your reply, altough I have to admit that I didnt entirely
understood how to actually caluculate the frequency.
Best regards, Moti |
|
| Back to top |
|
|
rickman
Guest
|
| Posted:
Mon Dec 06, 2004 10:40 pm Post subject:
Re: how to speed up my accumulator ?? |
|
|
Antti Lukats wrote:
| Quote: |
[lots of snipped]
Rick, hmmm... care to comment?
see synthesis and timing reports above :)
This shows that my approach will run twice as fast. It produces two
results rather than one and so can be constrained to require two clock
periods. You need to set your timing constraints to reflect that. The
only paths that don't run at the half clock rate are the output mux
running into accfast and the phase control signal. Set the path delay
on the accsingle and accdouble paths to be *two* clock periods (except
for the enable from phase).
:) ok, well your code "AS IS" did not synthesise so I tried mind guess an
fix to get it synthesize, posible making an error in the guess work.
YES, calculating 2 bits per clock is a solution, this is also what I
suggested in one of my earlier posts
I presented the synthesis (and timing) of the code "as you wrote" it (after
fix) I dont see the output mux in your code, and I did not add it either
generically I agree similar approuch (if code is correct) runs about twice
the speed
|
The output mux is the two assignments to accfast, one when phase is '0'
and the other when phase is '1'.
I took another look at the code and I don't see anything that would not
synthesize. What did the tool complain about?
| Quote: | But your timing numbers show both designs running at over 200 MHz which
is the OPs requirement, IIRC. Did you have to do any floorplanning?
Also, are these numbers post ROUTE or the output from synthesis? Timing
results from synthesis are worthless. I would like to see the details
on the critical path in each case.
I posted both synthesis estimate and post place and route timings, in any
case both approuch are 210MHz +
No floorplanning, just set clock constraint to 5ns nothing more
|
I only see one timing value for each example. What were the critical
paths in each design?
| Quote: | The logic for my code should be a minimum of 97 LUTs. Your result is
only 34 slices which is a maximum of 68 LUTs. I suspect there is some
problem so that the code does not synthesize correctly (possibly in the
code).
yes, possible i corrected your code incorrectly :(
I have not looked at the CLB details of the newer Xilinx FPGAs. An
adder still requires 1 LUT per bit, right? inc_value is a signal and
not a constant, right?
I used all signal 32 bit wide, inc_value as input port
|
That should work. Can you post the code you worked with?
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX |
|
| Back to top |
|
|
Antti Lukats
Guest
|
| Posted:
Mon Dec 06, 2004 11:05 pm Post subject:
Re: how to speed up my accumulator ?? |
|
|
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:41B49989.E7D9EFBC@yahoo.com...
| Quote: | Antti Lukats wrote:
[lots of snipped]
Rick, hmmm... care to comment?
see synthesis and timing reports above :)
[snip]
I used all signal 32 bit wide, inc_value as input port
That should work. Can you post the code you worked with?
--
Rick "rickman" Collins
|
Rick you can try your own code with XST it complains about the sll at least!
Maybe there is better(read proper fix) to main
the timings I posted I always posted synthesis estimae and post P&R timings
news posting did change the text aligne so was hard to read
below is what I used (fast-do-not-think-at-all .. fixed) from your code
----------------------------------------------------------------------------
---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dds is
Port ( clk : in std_logic;
rst : in std_logic;
inc_value : in std_logic_vector(31 downto 0);
fout : out std_logic);
end dds;
architecture Behavioral of dds is
signal accsingle : std_logic_vector(31 downto 0);
signal accdouble : std_logic_vector(31 downto 0);
signal accfast : std_logic_vector(31 downto 0);
signal phase : std_logic;
begin
process (clk, rst)
begin
if rst = '1' then
phase <= '0';
accsingle <= (others =>'0');
accdouble <= (others =>'0');
accfast <= (others =>'0');
elsif clk'event and clk ='1' then
phase <= not phase;
if (phase = '0') then
accfast <= accsingle;
else
accfast <= accdouble;
accsingle <= accdouble + inc_value;
accdouble <= accdouble + (inc_value(30 downto 0) & '0');
end if;
end if;
end process;
fout <= accfast (accfast'high);
end Behavioral;
------------------------------------------------------------------
below is DDSX in 2X mode there is no mux, 2 bits are calculated per clock
need external mux or serializer
------------------------------------------------------------------
//
// DDSX 2x Coyright 2004 OpenChip
//
// 2 DDS phase bits per single clock
// to be used with external (to this module) 2 bit
// deserializer running at 2X the clock of this module
//
`define DDSX_PHASE_WIDTH 32
`define DDSX_ACCU_WIDTH 32
`define DDSX_SERDES_WIDTH 2
module ddsx_2x(
clk,
rst,
load, // not used
phase, // phase increment
txdata, // output bits, need to be serialized at 2X clock
debug_next_accu // for simulation
);
input clk;
input rst;
input load;
input [`DDSX_PHASE_WIDTH-1:0] phase;
output [`DDSX_SERDES_WIDTH-1:0] txdata;
output [`DDSX_ACCU_WIDTH-1:0] debug_next_accu;
//
// Accumulator, on each clock advances 20 clocks !
//
reg [`DDSX_ACCU_WIDTH-1:0] accu;
//
// phase shifts for 2 steps
//
wire [`DDSX_PHASE_WIDTH :0] phase_2;
//
// Calc phase shifts for all steps
//
assign phase_2 = {phase[`DDSX_PHASE_WIDTH-1:0], 1'b0};
//
// Adder outputs
//
wire [`DDSX_ACCU_WIDTH-1:0] accu_p1;
wire [`DDSX_ACCU_WIDTH-1:0] accu_p2;
assign accu_p1 = accu + phase;
assign accu_p2 = accu + phase_2;
//
// Combine 2 next steps into one 2 bit word for high speed serdes
//
assign txdata[`DDSX_SERDES_WIDTH-1:0] = {
accu_p2 [`DDSX_ACCU_WIDTH-1],
accu_p1 [`DDSX_ACCU_WIDTH-1]};
//
// advance 2 clocks!
//
always @(posedge clk)
if (rst) accu <= `DDSX_ACCU_WIDTH'b0;
else accu <= accu_p2;
assign debug_next_accu = accu_p2;
endmodule |
|
| Back to top |
|
|
rickman
Guest
|
| Posted:
Tue Dec 07, 2004 12:12 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
Moti wrote:
| Quote: |
Hi Jhon,
thanks for your reply, altough I have to admit that I didnt entirely
understood how to actually caluculate the frequency.
Best regards, Moti
|
I think he is saying that you should expect the maximum deviations to be
n/m * Fref and n+1/m * Fref where n/m is the closest integer ratio that
gives you an exact frequency that the NCO can make without jitter.
Example: Fref is 1 MHz, Fout is 211 kHz, 32 bit accumulator. This gives
a step size of Fout/Fref * 2^32 = 906,238,099.456 ~= 906,238,099. This
will roll over the MSB on 4 or 5 clock pulses. So your Fout will be
composed of pulses of 4 clocks and pulses of 5 clocks with high and low
times of 2 and 3 clocks. The corresponding jitter will be... geeze,
this is hard isn't it?
I think you will get Fref/6 and Fref/2 as the range of jitter. I think
the formula should be...
Fmax = floor(Fref/(2*Fout)) * 0.5
Fmin = ceiling(Fref/(2*Fout)) * 0.5
Fjitter = Fmax-Fmin
I expect you will see main peaks in your FFT at Fmax and Fmin, no?
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX |
|
| Back to top |
|
|
Falk Brunner
Guest
|
| Posted:
Tue Dec 07, 2004 12:27 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag
news:41B4AF23.5CCD7DA7@yahoo.com...
| Quote: | Example: Fref is 1 MHz, Fout is 211 kHz, 32 bit accumulator. This gives
a step size of Fout/Fref * 2^32 = 906,238,099.456 ~= 906,238,099. This
will roll over the MSB on 4 or 5 clock pulses. So your Fout will be
composed of pulses of 4 clocks and pulses of 5 clocks with high and low
times of 2 and 3 clocks. The corresponding jitter will be... geeze,
this is hard isn't it?
|
If someone really want to break this down to the last bit, I got a PHD paper
here that is all about DDS, spectrum etc.
But its german, 3 Mb pdf.
If someone is intereted, drop me a mail.
Regards
Falk |
|
| Back to top |
|
|
rickman
Guest
|
| Posted:
Tue Dec 07, 2004 12:59 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
Antti Lukats wrote:
| Quote: |
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:41B49989.E7D9EFBC@yahoo.com...
Antti Lukats wrote:
[lots of snipped]
Rick, hmmm... care to comment?
see synthesis and timing reports above :)
[snip]
I used all signal 32 bit wide, inc_value as input port
That should work. Can you post the code you worked with?
--
Rick "rickman" Collins
Rick you can try your own code with XST it complains about the sll at least!
Maybe there is better(read proper fix) to main
the timings I posted I always posted synthesis estimae and post P&R timings
news posting did change the text aligne so was hard to read
below is what I used (fast-do-not-think-at-all .. fixed) from your code
----------------------------------------------------------------------------
---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dds is
Port ( clk : in std_logic;
rst : in std_logic;
inc_value : in std_logic_vector(31 downto 0);
fout : out std_logic);
end dds;
architecture Behavioral of dds is
signal accsingle : std_logic_vector(31 downto 0);
signal accdouble : std_logic_vector(31 downto 0);
signal accfast : std_logic_vector(31 downto 0);
signal phase : std_logic;
begin
process (clk, rst)
begin
if rst = '1' then
phase <= '0';
accsingle <= (others =>'0');
accdouble <= (others =>'0');
accfast <= (others =>'0');
elsif clk'event and clk ='1' then
phase <= not phase;
if (phase = '0') then
accfast <= accsingle;
else
accfast <= accdouble;
accsingle <= accdouble + inc_value;
accdouble <= accdouble + (inc_value(30 downto 0) & '0');
end if;
end if;
end process;
fout <= accfast (accfast'high);
end Behavioral;
|
This looks good to me. I found the sll in a book that warned about not
always being supported in synthesis since it was VHDL-1993 and still new
at that time. Jeeze, you would think XST would have gotten up the curve
by now.
But this code looks good to me. It should produce the following
hardware..
accsingle ====X=======X=======X=
accdouble ====X=======X=======X=
accfast X===X===X===X===X===X=
_ _ _ _ _ _
+--0<|---+ Clock | |_| |_| |_| |_| |_|
| | ___ ___ ___
| +---+ | Phase | |___| |___| |__
+-| |--+--------+------------------------+
| | | |
|> | | |
+---+ | V Left shift one bit |
+---------)-------------+ |
| | | |
| |\ | | |\ |
| | \ | | | \ |
-------+-| \ | +--| \ |
| \ | accsingle | \ | accdouble
inc_value \ | | +----+ \ | | +----+
| Quote: | |--)--| |--+ > |--)--| |--+
/ | | | | | / | | | | | |
| / +--|En | | | / +--|En | |
+--| / | | | +--| / | | | |
| | / |> | | | | / | |> | |
| |/ +----+ | | |/ | +----+ |
| | | | |
+---------------------)--+----------)----------+
| | |
| | |\--------+
| +---| \ accfast
| | | +----+
| | |--------| |---->
| | | | |
+-------------------------| / | |
|/ | |
|> |
+----+
The paths leading to accsingle and accdouble have two clock cycles to
settle and the paths to accfast has to settle in one clock cycle.
Looking at this, I realize that the accfast does not need the full 32
bits since only the MSb is used. So the LUT count should be 32 * 2 + 2
= 66.
The timing constraints must reflect the proper delays (2 clocks default
with one clock on all paths ending at accfast and all paths starting at
phase. Then the critical path will be one of the one clock paths which
should be able to be optimized to much faster than 200 MHz. Without the
timing constraints, the tools will analyze the adder paths as the
critical paths and report wrong timings.
The Spartan 3 CLB has input setup and clock to output delays of about
0.7 ns. With a routing delay of 1 ns between FFs in the same CLB, (I am
estimating a worst case routing delay, *really* worst case) this gives
2.4 ns or over 400 MHz. I guess the routing of the phase signal to the
32 bit registers may be a bit slower, but good floorplanning should
speed this up. Heck, I can get close to this speed in a relatively slow
and *ancient* ACEX part from Altera. I am sure the Spartan 3 can do
better.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX |
|
| Back to top |
|
|
mike_treseler@comcast.net
Guest
|
|
| Back to top |
|
|
Moti
Guest
|
| Posted:
Tue Dec 07, 2004 3:26 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
Hi Rickman,
Lots of thanks for the explanation and the numeric example.
I will defently use it and afterwards I will probably measure the
actual jitter frequency and compare it to the calculated results - when
I'll get the results I will post them (for those intersted)..
Thanks again, Moti. |
|
| Back to top |
|
|
Moti
Guest
|
| Posted:
Tue Dec 07, 2004 3:27 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
Hi Rickman,
Lots of thanks for the explanation and the numeric example.
I will defently use it and afterwards I will probably measure the
actual jitter frequency and compare it to the calculated results - when
I'll get the results I will post them (for those intersted)..
Thanks again, Moti. |
|
| Back to top |
|
|
Moti
Guest
|
| Posted:
Tue Dec 07, 2004 3:32 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
Hi Falk,
My german is pretty "rusty" :) so if the document is in .pdf format it
will very hard...
but if it's in a html format it can translated by google and then it
will be possible to read it!
Regards, Moti. |
|
| Back to top |
|
|
John_H
Guest
|
| Posted:
Tue Dec 07, 2004 4:06 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
It's involved...
With your example of 211kHz from a 1MHz reference, the ratio of
906,238,099/2^32 has closest fractions in order of worst to best of
1/5
4/19
23/109
211/1000
1987386/9418891
19873649/94187910
57633561/273144839
The offsets are the ideal frequency compared to the ratio frequency:
211 kHz - 200 kHz
211 kHz - 210.52632 kHz
211 kHz - 211.00917 kHz
211 kHz - 211 kHz... Here Excel starts to lose digits:
The difference between 906,238,099/2^32 and 906,238,099.456/2^32 is about
5.03e-10 at which point small amounts of jitter are lost. If the jitter at
that tiny offset is large, you will experience phase jumps when that beat
frequency is felt. There's no way to filter those with analog filters.
Your largest observed peaks in the spectrum will be at offsets of 11 kHz,
526 Hz, and 9.17 Hz. You should be able to see the 526 Hz modulating the
11kHz for spikes much smaller than the 11 kHz peak.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:41B4AF23.5CCD7DA7@yahoo.com...
| Quote: | Moti wrote:
Hi Jhon,
thanks for your reply, altough I have to admit that I didnt entirely
understood how to actually caluculate the frequency.
Best regards, Moti
I think he is saying that you should expect the maximum deviations to be
n/m * Fref and n+1/m * Fref where n/m is the closest integer ratio that
gives you an exact frequency that the NCO can make without jitter.
Example: Fref is 1 MHz, Fout is 211 kHz, 32 bit accumulator. This gives
a step size of Fout/Fref * 2^32 = 906,238,099.456 ~= 906,238,099. This
will roll over the MSB on 4 or 5 clock pulses. So your Fout will be
composed of pulses of 4 clocks and pulses of 5 clocks with high and low
times of 2 and 3 clocks. The corresponding jitter will be... geeze,
this is hard isn't it?
I think you will get Fref/6 and Fref/2 as the range of jitter. I think
the formula should be...
Fmax = floor(Fref/(2*Fout)) * 0.5
Fmin = ceiling(Fref/(2*Fout)) * 0.5
Fjitter = Fmax-Fmin
I expect you will see main peaks in your FFT at Fmax and Fmin, no?
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX |
|
|
| Back to top |
|
|
Jim Granville
Guest
|
| Posted:
Tue Dec 07, 2004 7:34 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
John_H wrote:
| Quote: | It's involved...
With your example of 211kHz from a 1MHz reference, the ratio of
906,238,099/2^32 has closest fractions in order of worst to best of
1/5
4/19
23/109
211/1000
1987386/9418891
19873649/94187910
57633561/273144839
The offsets are the ideal frequency compared to the ratio frequency:
211 kHz - 200 kHz
211 kHz - 210.52632 kHz
211 kHz - 211.00917 kHz
211 kHz - 211 kHz... Here Excel starts to lose digits:
The difference between 906,238,099/2^32 and 906,238,099.456/2^32 is about
5.03e-10 at which point small amounts of jitter are lost. If the jitter at
that tiny offset is large, you will experience phase jumps when that beat
frequency is felt. There's no way to filter those with analog filters.
Your largest observed peaks in the spectrum will be at offsets of 11 kHz,
526 Hz, and 9.17 Hz. You should be able to see the 526 Hz modulating the
11kHz for spikes much smaller than the 11 kHz peak.
|
Good example maths, but is the principle right ?
For the example of 211KHz from 1Mhz, you have 1us quantize, and so will
be able to generate 4us, or 5us periods, giving 250KHz and 200KHz.
Over many cycles, the 'wobbling' between these two will average to
211KHz. The more cycles, the better the match to 211KHz.
Over a 6 cycle snapshot, you might see 5@200, 1@250, and Favge 208.33Khz
That's appx one part in 77 too slow.
This 6 cycle frame has a freq of 34.6KHz
Next frame group would be (eg)
every 79 cycles, to see => 14 @ 250KHz, 65@ 200KHz => 210.76923Khz,
Error is now one part in 1000, and this finer frame is 2.65KHz
( etc ) as over wider frame snap-shots, the average frequency gets
closer to the 211KHz ideal.
So I'd expect to see, on a spectrum analyser, 200KHz, (Dominant) 250KHz
and 34.6KHz and 2.65KHz (etc) energies.
-jg |
|
| Back to top |
|
|
Allan Herriman
Guest
|
| Posted:
Tue Dec 07, 2004 8:58 am Post subject:
Re: how to speed up my accumulator ?? |
|
|
On Tue, 07 Dec 2004 15:34:36 +1300, Jim Granville
<no.spam@designtools.co.nz> wrote:
| Quote: | John_H wrote:
It's involved...
With your example of 211kHz from a 1MHz reference, the ratio of
906,238,099/2^32 has closest fractions in order of worst to best of
1/5
4/19
23/109
211/1000
1987386/9418891
19873649/94187910
57633561/273144839
The offsets are the ideal frequency compared to the ratio frequency:
211 kHz - 200 kHz
211 kHz - 210.52632 kHz
211 kHz - 211.00917 kHz
211 kHz - 211 kHz... Here Excel starts to lose digits:
The difference between 906,238,099/2^32 and 906,238,099.456/2^32 is about
5.03e-10 at which point small amounts of jitter are lost. If the jitter at
that tiny offset is large, you will experience phase jumps when that beat
frequency is felt. There's no way to filter those with analog filters.
Your largest observed peaks in the spectrum will be at offsets of 11 kHz,
526 Hz, and 9.17 Hz. You should be able to see the 526 Hz modulating the
11kHz for spikes much smaller than the 11 kHz peak.
Good example maths, but is the principle right ?
For the example of 211KHz from 1Mhz, you have 1us quantize, and so will
be able to generate 4us, or 5us periods, giving 250KHz and 200KHz.
Over many cycles, the 'wobbling' between these two will average to
211KHz. The more cycles, the better the match to 211KHz.
Over a 6 cycle snapshot, you might see 5@200, 1@250, and Favge 208.33Khz
That's appx one part in 77 too slow.
This 6 cycle frame has a freq of 34.6KHz
Next frame group would be (eg)
every 79 cycles, to see => 14 @ 250KHz, 65@ 200KHz => 210.76923Khz,
Error is now one part in 1000, and this finer frame is 2.65KHz
( etc ) as over wider frame snap-shots, the average frequency gets
closer to the 211KHz ideal.
So I'd expect to see, on a spectrum analyser, 200KHz, (Dominant) 250KHz
and 34.6KHz and 2.65KHz (etc) energies.
|
Did you actually plug it in to a spectrum analyser and see those
tones?
Ten highest spurious tones:
55.000kHz -11.4dBc
367.000kHz -16.7dBc
101.000kHz -17.0dBc
165.000kHz -22.4dBc
9.000kHz -22.9dBc
257.000kHz -24.1dBc
321.000kHz -25.1dBc
147.000kHz -25.8dBc
119.000kHz -27.4dBc
37.000kHz -27.7dBc
Regards,
Allan |
|
| Back to top |
|
|
|
|
|
|
FAQ
Memberlist
Register
Profile
Log in to check your private messages
Log in