FPGA as host for a USB peripheral

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FPGA as host for a USB peripheral

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Jacob Bower
Guest

Posted: Mon Dec 06, 2004 8:51 pm Post subject: FPGA as host for a USB peripheral

Hi, I was wondering if anyone in this group can provide some insight as to how hard it might be to get an FPGA to act as a USB host, for collecting data at quite a high-bandwidth. Particularly can this reasonably be done at all with a completely hardware implementation, possibly with an external embedded USB host controller. Or would I be much better off using some kind of soft-core CPU to collect and format data from the USB peripheral due complexity of driving an embedded USB host controller? Thanks, - Jake

Rudolf Usselmann
Guest

Posted: Tue Dec 07, 2004 12:50 pm Post subject: Re: FPGA as host for a USB peripheral

Jacob Bower wrote:

Quote:

Hi,

I was wondering if anyone in this group can provide some insight as to how
hard it might be to get an FPGA to act as a USB host, for collecting data
at quite a high-bandwidth. Particularly can this reasonably be done at all
with a completely hardware implementation, possibly with an external
embedded USB host controller. Or would I be much better off using some
kind of soft-core CPU to collect and format data from the USB peripheral
due complexity of driving an embedded USB host controller?

Thanks,
- Jake

It's doable in hardware, but extremely complex. The enumeration
process needs quite a bit of decisions making.

However, once the enumeration is complete, there is no reason
why other endpoints (non-zero) could not be 100% hardware
interface pipes.

Not sure what your interpretation of "high bandwidth" is, but
USB 2.0 only goes to 480 Mbits/sec, or about 60Mbyes/sec. So
it should be quite trivial to do this in FPGA. However you
will need a High Speed USB PHY.

Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

Jacob Bower
Guest

Posted: Tue Dec 07, 2004 3:53 pm Post subject: Re: FPGA as host for a USB peripheral

Rudi,

Quote:

It's doable in hardware, but extremely complex. The enumeration
process needs quite a bit of decisions making.

Is it possible to "cheat" and reduce this complexity, if I know that I will
literally only ever have exactly zero one specific device connected?

Are there any free/commercial IP cores around that could help with this?

Quote:

It doesn't matter if it can be done completely in hardware. The only reason
I wanted to mention high-bandwidth was for the case where I would have to
use a soft-core processor as the complexity of driving the USB host
controller is too great to be feasible in anything but software. Then of
course I would have the consideration that the processor would need to be
fast enough to handle passing through the data.

Thanks for the suggestions,
- Jake

Antti Lukats
Guest

Posted: Tue Dec 07, 2004 9:35 pm Post subject: Re: FPGA as host for a USB peripheral

"Jacob Bower" <jacob.bower@gmail.com> wrote in message
news:slrncrbkfa.pma.jab00@sprite.doc.ic.ac.uk...

Quote:

Rudi,

It's doable in hardware, but extremely complex. The enumeration
process needs quite a bit of decisions making.

Is it possible to "cheat" and reduce this complexity, if I know that I
will
literally only ever have exactly zero one specific device connected?

that makes it a lot simpler, in very minimal case you possible only need
setAddress and setConfiguration to put the device in "configured" state.
After that you possible can do the special tasks for the gadget as you need
it.

If you need different devices to be supported or even worse need to support
hubs then the host enumeratio would be way more complex.

Quote:

Are there any free/commercial IP cores around that could help with this?

commercial sure are available, but I guess none of the existing ones is

directly optimized to support one gadget and doing it in fpga directly.
Choices are
1) SoC + bus peripheral USB host ip core
2) same as above but with some dedicated logic that "routes" some
endpoints/buffers to on fpga dedicated handler to achive maximum bandwidth
and bypass the cpu directly. - this is most likely not needed

free, hm I think there is no free HS host as of today

Quote:

Not sure what your interpretation of "high bandwidth" is, but
USB 2.0 only goes to 480 Mbits/sec, or about 60Mbyes/sec. So
it should be quite trivial to do this in FPGA. However you
will need a High Speed USB PHY.

It doesn't matter if it can be done completely in hardware. The only
reason
I wanted to mention high-bandwidth was for the case where I would have to
use a soft-core processor as the complexity of driving the USB host
controller is too great to be feasible in anything but software. Then of
course I would have the consideration that the processor would need to be
fast enough to handle passing through the data.

Thanks for the suggestions,
- Jake

yes, if you need the absolute maximum possible bandwidth then any fpga
softcore processor would have it hard time shuffling the data, most likely
there would be some "gaps" of time when the cpu has not managed to
fill/empty some buffer at the time when the usb bus would be ready. If the
usb ip core uses dma and data is mostly in big chunks the soft overhead is
very small, if the cou has todo something between packets (and if packets
are small) then software overhead increases.

Antti

Antonio Pasini
Guest

Posted: Wed Dec 08, 2004 2:00 am Post subject: Re: FPGA as host for a USB peripheral

Quote:

Is it possible to "cheat" and reduce this complexity, if I know that I
will
literally only ever have exactly zero one specific device connected?

I'm investigating options for something quite similar.
Please keep in touch, to exchange experiences!

Now I'm doing the peripheral side, but sooner or later I will have no more
excuses to delay the difficult part :-).
I did my best to avoid having doing this, but finally I was persuaded was
the only reasonable way, given marketing / commercial constraints.

Reducing options to just your custom device, without any hub, seems much
more easier. In my case, I can and surely will. Absolutely.
The host stack itself is way easier, if you do not have to handle all hub
stuff, also.

I'll use an FPGA together with a softcore (Mblaze) for stack handling. Data
will come as an isochronous HS stream, so I'll try to route them inside the
FPGA directly to the logic that needs them, avoiding the softcore.

Decision left is whether to use an external embedded HS host (not so many,
here, for true HS. Philips ? TransDimensions ?) or a HS host core inside the
FPGA. I'd prefer the second, of course, but usually this kind of cores costs
an arm and a leg.

Check www.asics.ws, they are quite experienced, and as you see Rudolf
Usselman reads and follows this newsgroup.
I think Antti Lukats can help you, also, it's rather knowledgeable in USB +
fpga.

In any case, please share your experiences with this group. I'll surely will
(if going okay... otherwise, i'll be too busy searching for a new job :-)

Standard disclaimer applies, here: I have no connection to them. Just
thinking to calling them for help, given that they seems the best option, in
my opinion (as today).

Rudolf Usselmann
Guest

Posted: Wed Dec 08, 2004 9:26 am Post subject: Re: FPGA as host for a USB peripheral

Jacob Bower wrote:

Quote:

Rudi,

It's doable in hardware, but extremely complex. The enumeration
process needs quite a bit of decisions making.

Is it possible to "cheat" and reduce this complexity, if I know that I
will literally only ever have exactly zero one specific device connected?

Jake,

Yes, thats definitely possible. You could skip a lot of the steps
if you know the device that will be attached.

Quote:

Are there any free/commercial IP cores around that could help with this?

We only have commercial host controller IP Cores. Check our web
site for more info.

Quote:

Not sure what your interpretation of "high bandwidth" is, but
USB 2.0 only goes to 480 Mbits/sec, or about 60Mbyes/sec. So
it should be quite trivial to do this in FPGA. However you
will need a High Speed USB PHY.

It doesn't matter if it can be done completely in hardware. The only
reason I wanted to mention high-bandwidth was for the case where I would
have to use a soft-core processor as the complexity of driving the USB
host controller is too great to be feasible in anything but software. Then
of course I would have the consideration that the processor would need to
be fast enough to handle passing through the data.

Well, the control path and data path can be separate. You can
have a small low end MCU doing the enumeration, and a pure
hardware based data pipe for the endpoints. It all depends on
how robust you rimplementation has to be ...

Quote:

Thanks for the suggestions,
- Jake

Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

valentin tihomirov
Guest

Posted: Thu Dec 09, 2004 4:51 pm Post subject: Re: FPGA as host for a USB peripheral

Quote:

Is there a special USB slave device that enumerates and configures hosts?

Ulf Samuelsson
Guest

Posted: Tue Dec 14, 2004 4:27 am Post subject: Re: FPGA as host for a USB peripheral

"Jacob Bower" <jacob.bower@gmail.com> skrev i meddelandet
news:slrncr9his.c73.jab00@sprite.doc.ic.ac.uk...

Quote:

Hi,

I was wondering if anyone in this group can provide some insight as to how
hard it might be to get an FPGA to act as a USB host, for collecting data
at quite a high-bandwidth. Particularly can this reasonably be done at all
with a completely hardware implementation, possibly with an external
embedded USB host controller. Or would I be much better off using some
kind
of soft-core CPU to collect and format data from the USB peripheral due
complexity of driving an embedded USB host controller?

Thanks,
- Jake

Question is if you can do it cost effectively in an FPGA.
If you take an intelligent USB Host like the AT43USB380, you still
need an external micro with about 64 kB of memory just for a single driver
(for Mass Storage). Maybe your device class is simpler
but uyou probably need a soft MCU and around 16 kB
of code just to run the USB Host Stack without any device class.

If it is point to point, why need USB at all?

--
Best Regards,
Ulf Samuelsson ulf@a-t-m-e-l.com
This is a personal view which may or may not be
share by my Employer Atmel Nordic AB

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