default changes with new release

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default changes with new release

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colin_toogood@yahoo.com
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Posted: Fri Dec 10, 2004 7:19 pm Post subject: default changes with new release

All Is it just me or does the whole world hate it when the defaults on a new release changes. ISE 6.3 now defaults all IO to lvcmos_25. I now have a whole host of vhdl that I maintain that will not just compile. If I need to make a trivial change then I have to check carefully. I can live with this today because I know that I need to do this. Next time though I may or may not remember this new setting and I will not remember whether the code has been modified to give me lvcmos33 (the old default). On a somewhat related subject I have fiddled with setting the iostandard in VHDL. There are examples of instantiating an IOB and then setting the IOB to whatever standard but what about a simple net out of the top level entity with IOB created by synthesis. I presume that this is trivial but I haven't been successfull. Can someone please help? Colin

Brian Davis
Guest

Posted: Sat Dec 11, 2004 8:05 am Post subject: Re: default changes with new release

Colin wrote:

Quote:

On a somewhat related subject I have fiddled with setting the
iostandard in VHDL. <snip> but what about a simple net out of
the top level entity with IOB created by synthesis.

See example below

Brian

--
-- I/O pin attribute example for Xilinx Spartan3 eval kit
--
entity ram_test is
port
(
--
-- default clock osc.
--
clk50_in : in std_logic;

--
-- 4 pushbuttons, 8 slide switches
--
pb : in std_logic_vector(3 downto 0);
sw : in std_logic_vector(7 downto 0);

--
-- individual leds
--
led : out std_logic_vector(7 downto 0);

--
-- muxed seven segment LEDs
--
digit : out std_logic_vector(3 downto 0);

seg_a : out std_logic;
seg_b : out std_logic;
seg_c : out std_logic;
seg_d : out std_logic;
seg_e : out std_logic;
seg_f : out std_logic;
seg_g : out std_logic;
seg_dp : out std_logic;

--
-- SRAM signals
--

--
-- shared control and address
--
ram_we_l : out std_logic;
ram_oe_l : out std_logic;
ram_addr : out std_logic_vector(17 downto 0);

--
-- per-bank SRAM signals
--
ram_a_dat : inout std_logic_vector(15 downto 0);
ram_a_ce_l : out std_logic;
ram_a_ub : out std_logic;
ram_a_lb : out std_logic;

ram_b_dat : inout std_logic_vector(15 downto 0);
ram_b_ce_l : out std_logic;
ram_b_ub : out std_logic;
ram_b_lb : out std_logic

);

attribute loc : string ;
attribute slew : string ;
attribute drive : string ;
attribute iostandard : string ;

attribute loc of clk50_in : signal is "t9";
attribute iostandard of clk50_in : signal is "LVCMOS33";

attribute loc of pb : signal is "l14,l13,m14,m13";
attribute iostandard of pb : signal is "LVCMOS33";

attribute loc of sw : signal is
"k13,k14,j13,j14,h13,h14,g12,f12";
attribute iostandard of sw : signal is "LVCMOS33";

attribute loc of led : signal is
"p11,p12,n12,p13,n14,l12,p14,k12";
attribute iostandard of led : signal is "LVCMOS33";
attribute slew of led : signal is "SLOW";

attribute loc of digit : signal is "e13,f14,g14,d14";
attribute iostandard of digit : signal is "LVCMOS33";
attribute slew of digit : signal is "SLOW";

attribute loc of seg_a : signal is "e14";
attribute iostandard of seg_a : signal is "LVCMOS33";
attribute slew of seg_a : signal is "SLOW";

attribute loc of seg_b : signal is "g13";
attribute iostandard of seg_b : signal is "LVCMOS33";
attribute slew of seg_b : signal is "SLOW";

attribute loc of seg_c : signal is "n15";
attribute iostandard of seg_c : signal is "LVCMOS33";
attribute slew of seg_c : signal is "SLOW";

attribute loc of seg_d : signal is "p15";
attribute iostandard of seg_d : signal is "LVCMOS33";
attribute slew of seg_d : signal is "SLOW";

attribute loc of seg_e : signal is "r16";
attribute iostandard of seg_e : signal is "LVCMOS33";
attribute slew of seg_e : signal is "SLOW";

attribute loc of seg_f : signal is "f13";
attribute iostandard of seg_f : signal is "LVCMOS33";
attribute slew of seg_f : signal is "SLOW";

attribute loc of seg_g : signal is "n16";
attribute iostandard of seg_g : signal is "LVCMOS33";
attribute slew of seg_g : signal is "SLOW";

attribute loc of seg_dp : signal is "p16";
attribute iostandard of seg_dp : signal is "LVCMOS33";
attribute slew of seg_dp : signal is "SLOW";

attribute loc of ram_addr : signal is
"l3,k5,k3,j3,j4,h4,h3,g5,e4,e3,f4,f3,g4,l4,m3,m4,n3,l5";
attribute iostandard of ram_addr : signal is "LVCMOS33";
attribute slew of ram_addr : signal is "SLOW";
attribute drive of ram_addr : signal is "24";

attribute loc of ram_we_l : signal is "g3";
attribute iostandard of ram_we_l : signal is "LVCMOS33";
attribute slew of ram_we_l : signal is "FAST";
attribute drive of ram_we_l : signal is "24";

attribute loc of ram_oe_l : signal is "k4";
attribute iostandard of ram_oe_l : signal is "LVCMOS33";
attribute slew of ram_oe_l : signal is "SLOW";
attribute drive of ram_oe_l : signal is "12";

attribute loc of ram_a_dat : signal is
"r1,p1,l2,j2,h1,f2,p8,d3,b1,c1,c2,r5,t5,r6,t8,n7";
attribute iostandard of ram_a_dat : signal is "LVCMOS33";
attribute slew of ram_a_dat : signal is "SLOW";
attribute drive of ram_a_dat : signal is "6";

attribute loc of ram_a_ce_l : signal is "p7";
attribute iostandard of ram_a_ce_l : signal is "LVCMOS33";
attribute slew of ram_a_ce_l : signal is "SLOW";
attribute drive of ram_a_ce_l : signal is "12";

attribute loc of ram_a_lb : signal is "p6";
attribute iostandard of ram_a_lb : signal is "LVCMOS33";
attribute slew of ram_a_lb : signal is "SLOW";
attribute drive of ram_a_lb : signal is "12";

attribute loc of ram_a_ub : signal is "t4";
attribute iostandard of ram_a_ub : signal is "LVCMOS33";
attribute slew of ram_a_ub : signal is "SLOW";
attribute drive of ram_a_ub : signal is "12";

attribute loc of ram_b_dat : signal is
"n1,m1,k2,c3,f5,g1,e2,d2,d1,e1,g2,j1,k1,m2,n2,p2";
attribute iostandard of ram_b_dat : signal is "LVCMOS33";
attribute slew of ram_b_dat : signal is "SLOW";
attribute drive of ram_b_dat : signal is "6";

attribute loc of ram_b_ce_l : signal is "n5";
attribute iostandard of ram_b_ce_l : signal is "LVCMOS33";
attribute slew of ram_b_ce_l : signal is "SLOW";
attribute drive of ram_b_ce_l : signal is "12";

attribute loc of ram_b_lb : signal is "p5";
attribute iostandard of ram_b_lb : signal is "LVCMOS33";
attribute slew of ram_b_lb : signal is "SLOW";
attribute drive of ram_b_lb : signal is "12";

attribute loc of ram_b_ub : signal is "r4";
attribute iostandard of ram_b_ub : signal is "LVCMOS33";
attribute slew of ram_b_ub : signal is "SLOW";
attribute drive of ram_b_ub : signal is "12";

end ram_test;

Brian Davis
Guest

Posted: Sat Dec 11, 2004 9:07 am Post subject: Re: default changes with new release

Colin wrote:

Quote:

On a somewhat related subject I have fiddled with setting the
iostandard in VHDL. <snip> but what about a simple net out of
the top level entity with IOB created by synthesis.

See example below

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