| Author |
Message |
Elder Costa
Guest
|
 Posted:
Sat Dec 11, 2004 3:41 am Post subject:
Inferring dual port RAMs with different bus widths. |
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Hello folks.
I have implemented the entity bellow by instantciating a dual ported
block RAM with different bus widths (RAMB16_S18_S36 - I am developing
for Virtex II or Spartan 3). Whereas it is relatively simple to do it by
instantiacing the component from Xilinx library, I wonder if there is a
way to code the module so that Xst infers the block RAM. I tried in one
or two ways but it used logic in slices instead of BRAM and it required
a lot of logic for a 1kib RAM. Could somebody give a hint on this? I
looked at Xilinx documentation and couldn't find an example for this
particular problem.
entity gaintab is
Port (
-- ports de acesso do processador
i_ProcAddr : in std_logic_vector(9 downto 0);
i_ProcDataIn : in std_logic_vector(15 downto 0);
i_ProcWr : in std_logic;
i_ProcEn : in std_logic;
i_ProcClk : in std_logic;
o_ProcDataOut : out std_logic_vector(15 downto 0);
-- ports de acesso interno (fpga)
i_FpgaAddr : in std_logic_vector(6 downto 0);
i_FpgaClk : in std_logic;
o_FpgaDataOut : out std_logic_vector(31 downto 0)
);
end gaintab;
TIA.
Elder. |
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Simon Peacock
Guest
|
| Posted:
Sat Dec 11, 2004 8:41 am Post subject:
Re: Inferring dual port RAMs with different bus widths. |
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|
from what I understand.. you cant infer different bus widths sorry.. Not
even Synplify can
Simon
"Elder Costa" <elder.costa@terra.com.br> wrote in message
news:31umvgF3h46qjU1@individual.net...
| Quote: | Hello folks.
I have implemented the entity bellow by instantciating a dual ported
block RAM with different bus widths (RAMB16_S18_S36 - I am developing
for Virtex II or Spartan 3). Whereas it is relatively simple to do it by
instantiacing the component from Xilinx library, I wonder if there is a
way to code the module so that Xst infers the block RAM. I tried in one
or two ways but it used logic in slices instead of BRAM and it required
a lot of logic for a 1kib RAM. Could somebody give a hint on this? I
looked at Xilinx documentation and couldn't find an example for this
particular problem.
entity gaintab is
Port (
-- ports de acesso do processador
i_ProcAddr : in std_logic_vector(9 downto 0);
i_ProcDataIn : in std_logic_vector(15 downto 0);
i_ProcWr : in std_logic;
i_ProcEn : in std_logic;
i_ProcClk : in std_logic;
o_ProcDataOut : out std_logic_vector(15 downto 0);
-- ports de acesso interno (fpga)
i_FpgaAddr : in std_logic_vector(6 downto 0);
i_FpgaClk : in std_logic;
o_FpgaDataOut : out std_logic_vector(31 downto 0)
);
end gaintab;
TIA.
Elder.
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Javier Castillo
Guest
|
| Posted:
Mon Dec 13, 2004 8:54 am Post subject:
Re: Inferring dual port RAMs with different bus widths. |
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|
Hello:
If you inferr a ram from a synthesis tool it always be done using
slices configured as RAM, to use block RAM in a Xilinx FPGA you must
generate it using Coregen and adding the .xco file to your project in
ISE.
Regards
Javier Castillo
jcastillo@opensocdesign.com
www.opensocdesign.com
Elder Costa <elder.costa@terra.com.br> wrote in news:31umvgF3h46qjU1
@individual.net:
| Quote: | Hello folks.
I have implemented the entity bellow by instantciating a dual ported
block RAM with different bus widths (RAMB16_S18_S36 - I am developing
for Virtex II or Spartan 3). Whereas it is relatively simple to do it
by
instantiacing the component from Xilinx library, I wonder if there is
a
way to code the module so that Xst infers the block RAM. I tried in
one
or two ways but it used logic in slices instead of BRAM and it
required
a lot of logic for a 1kib RAM. Could somebody give a hint on this? I
looked at Xilinx documentation and couldn't find an example for this
particular problem.
entity gaintab is
Port (
-- ports de acesso do processador
i_ProcAddr : in std_logic_vector(9 downto 0);
i_ProcDataIn : in std_logic_vector(15 downto 0);
i_ProcWr : in std_logic;
i_ProcEn : in std_logic;
i_ProcClk : in std_logic;
o_ProcDataOut : out std_logic_vector(15 downto 0);
-- ports de acesso interno (fpga)
i_FpgaAddr : in std_logic_vector(6 downto 0);
i_FpgaClk : in std_logic;
o_FpgaDataOut : out std_logic_vector(31 downto 0)
);
end gaintab;
TIA.
Elder.
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Mike Treseler
Guest
|
| Posted:
Mon Dec 13, 2004 7:22 pm Post subject:
Re: Inferring dual port RAMs with different bus widths. |
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|
Javier Castillo wrote:
| Quote: | If you inferr a ram from a synthesis tool it always be done using
slices configured as RAM, to use block RAM in a Xilinx FPGA you must
generate it using Coregen and adding the .xco file to your project in
ISE.
|
Block RAM can be inferred by synthesis tools.
Dual port ram with one read and one write port
can be inferred by synthesis tools.
True dual port RAM with two read/write ports
requires a device-specific instance.
-- Mike Treseler |
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Elder Costa
Guest
|
| Posted:
Tue Dec 14, 2004 2:06 am Post subject:
Re: Inferring dual port RAMs with different bus widths. |
|
|
Elder Costa wrote:
| Quote: | Hello folks.
I have implemented the entity bellow by instantciating a dual ported
block RAM with different bus widths (RAMB16_S18_S36 - I am developing
for Virtex II or Spartan 3). Whereas it is relatively simple to do it by
instantiacing the component from Xilinx library, I wonder if there is a
way to code the module so that Xst infers the block RAM. I tried in one
or two ways but it used logic in slices instead of BRAM and it required
a lot of logic for a 1kib RAM. Could somebody give a hint on this? I
looked at Xilinx documentation and couldn't find an example for this
particular problem.
entity gaintab is
Port (
-- ports de acesso do processador
i_ProcAddr : in std_logic_vector(9 downto 0);
i_ProcDataIn : in std_logic_vector(15 downto 0);
i_ProcWr : in std_logic;
i_ProcEn : in std_logic;
i_ProcClk : in std_logic;
o_ProcDataOut : out std_logic_vector(15 downto 0);
-- ports de acesso interno (fpga)
i_FpgaAddr : in std_logic_vector(6 downto 0);
i_FpgaClk : in std_logic;
o_FpgaDataOut : out std_logic_vector(31 downto 0)
);
end gaintab;
TIA.
Elder.
|
I've been able to make the synthesizer to infer the RAM as above but I
had to create an entity similar to the above but with the same bus width
in every data port and then by instanciating it twice. Somewhat tricky
though.
Regards.
Elder. |
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