LUT and MUXF5 placement

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LUT and MUXF5 placement

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Jim George
Guest

Posted: Mon Dec 13, 2004 4:14 am Post subject: LUT and MUXF5 placement

Hello, I wanted to know how you instruct MAP to place an LUT and a MUXF5 into the same slice. Looking at the V2 Datasheet, it seems to be an allowed combination. However, I get a MAP error stating that the LUT and MUXF5 cannot share the same slice. I'm specifiying the constraints within the VHDL (again, inspired by Ray Andraka). Thanks! -Jim

Bret Wade
Guest

Posted: Mon Dec 13, 2004 6:51 am Post subject: Re: LUT and MUXF5 placement

Jim George wrote:

Quote:

Hello,
I wanted to know how you instruct MAP to place an LUT and a MUXF5
into the same slice. Looking at the V2 Datasheet, it seems to be an
allowed combination. However, I get a MAP error stating that the LUT and
MUXF5 cannot share the same slice. I'm specifiying the constraints
within the VHDL (again, inspired by Ray Andraka).
Thanks!
-Jim

Hi Jim,

Without knowing what the error is, it's difficult to comment. It sounds
as if you've successfully specified the constraints, but the packer is
rejecting the constraints for some reason. If the MAP error begins with
"ERROR:Pack:679" then that's the case. The first line in the error
message identifies the failing constraint. This is followed by a list of
symbols involved. The last line indicates the reason for the failure and
this is what you should focus on.

Some times there is a connectivity restriction involved that is not
obvious until you become very familiar with the possible slice
configurations. Try using the Logic Block Editor inside FPGA Editor to
assemble a slice equivalent to your logic. The restriction should become
apparent then.

Another possibility is that it is possible to pack the logic into one
slice, but the packer isn't getting it right. In that case, it might
help to use BEL constraints to be more specific about how the slice
should be assembled. Possible values are F, G, CYMUXF, CYMUXG, XORF,
XORG, FFX, FFY.

Bret

Jim George
Guest

Posted: Mon Dec 13, 2004 6:56 am Post subject: Re: LUT and MUXF5 placement

Bret Wade wrote:

Quote:

Jim George wrote:

Hello,
I wanted to know how you instruct MAP to place an LUT and a MUXF5
into the same slice. Looking at the V2 Datasheet, it seems to be an
allowed combination. However, I get a MAP error stating that the LUT
and MUXF5 cannot share the same slice. I'm specifiying the constraints
within the VHDL (again, inspired by Ray Andraka).
Thanks!
-Jim

Hi Jim,

Without knowing what the error is, it's difficult to comment. It sounds
as if you've successfully specified the constraints, but the packer is
rejecting the constraints for some reason. If the MAP error begins with
"ERROR:Pack:679" then that's the case. The first line in the error
message identifies the failing constraint. This is followed by a list of
symbols involved. The last line indicates the reason for the failure and
this is what you should focus on.

Some times there is a connectivity restriction involved that is not
obvious until you become very familiar with the possible slice
configurations. Try using the Logic Block Editor inside FPGA Editor to
assemble a slice equivalent to your logic. The restriction should become
apparent then.

Another possibility is that it is possible to pack the logic into one
slice, but the packer isn't getting it right. In that case, it might
help to use BEL constraints to be more specific about how the slice
should be assembled. Possible values are F, G, CYMUXF, CYMUXG, XORF,
XORG, FFX, FFY.

Bret

Thanks for the quick reply. OK, I was in the tearing-out-hair stage when
I last posted, here's what it should have said: I'm trying to pack in an
SRL16 and a LUT into the same slice, then use a MUXF5 on the output of
the two. Is this allowed? I've written some example code similar to the
one which caused the problem:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity example is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
clk : in std_logic;
sel : in std_logic;
y : out std_logic);
end example;
architecture Behavioral of example is
attribute RLOC: string;
attribute U_SET: string;
signal internal_1, internal_2 : std_logic;
signal len : std_logic_vector(3 downto 0);
attribute RLOC of the_lut: label is "X0" & "Y0";
attribute U_SET of the_lut: label is "set";
attribute RLOC of the_srl: label is "X0" & "Y0";
attribute U_SET of the_srl: label is "set";
attribute RLOC of the_muxf5: label is "X0" & "Y0";
attribute U_SET of the_muxf5: label is "set";
begin
len <= "1110";
the_lut: lut2_l
generic map (init => X"8")
port map (
i0 => a,
i1 => b,
lo => internal_1
);
the_srl: SRL16
port map (
q => internal_2,
a0 => len(0),
a1 => len(1),
a2 => len(2),
a3 => len(3),
clk => clk,
d => c
);
the_muxf5: MUXF5
port map (
i0 => internal_1,
i1 => internal_2,
o => y,
s => sel
);
end Behavioral;

The exact error from MAP is:

ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=set,
RLOC=X0Y0) which require the combination of the following symbols into a
single SLICE component:
Shift symbol "the_srl/SRL16E" (Output Signal = internal_2)
LUT symbol "the_lut" (Output Signal = the_lut/O)
MUXF5 symbol "the_muxf5" (Output Signal = y_OBUF)
The function generator the_srl/SRL16E is unable to be placed in the
G position because the output signal doesn't match other symbols' use of
the G signal. The signal the_lut/O already uses G. Please correct the
design constraints accordingly.

I'm sure I'm doing something really dumb here... but will using BEL
help fix this? Oh, and I'm using WebPack, so I dont have FPGA Editor.
Thank you.
-Jim

Bret Wade
Guest

Posted: Mon Dec 13, 2004 12:15 pm Post subject: Re: LUT and MUXF5 placement

Jim George wrote:

Quote:

Thanks for the quick reply. OK, I was in the tearing-out-hair stage when
I last posted, here's what it should have said: I'm trying to pack in an
SRL16 and a LUT into the same slice, then use a MUXF5 on the output of
the two. Is this allowed? I've written some example code similar to the
one which caused the problem:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity example is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
clk : in std_logic;
sel : in std_logic;
y : out std_logic);
end example;
architecture Behavioral of example is
attribute RLOC: string;
attribute U_SET: string;
signal internal_1, internal_2 : std_logic;
signal len : std_logic_vector(3 downto 0);
attribute RLOC of the_lut: label is "X0" & "Y0";
attribute U_SET of the_lut: label is "set";
attribute RLOC of the_srl: label is "X0" & "Y0";
attribute U_SET of the_srl: label is "set";
attribute RLOC of the_muxf5: label is "X0" & "Y0";
attribute U_SET of the_muxf5: label is "set";
begin
len <= "1110";
the_lut: lut2_l
generic map (init => X"8")
port map (
i0 => a,
i1 => b,
lo => internal_1
);
the_srl: SRL16
port map (
q => internal_2,
a0 => len(0),
a1 => len(1),
a2 => len(2),
a3 => len(3),
clk => clk,
d => c
);
the_muxf5: MUXF5
port map (
i0 => internal_1,
i1 => internal_2,
o => y,
s => sel
);
end Behavioral;

The exact error from MAP is:

ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=set,
RLOC=X0Y0) which require the combination of the following symbols into a
single SLICE component:
Shift symbol "the_srl/SRL16E" (Output Signal = internal_2)
LUT symbol "the_lut" (Output Signal = the_lut/O)
MUXF5 symbol "the_muxf5" (Output Signal = y_OBUF)
The function generator the_srl/SRL16E is unable to be placed in the G
position because the output signal doesn't match other symbols' use of
the G signal. The signal the_lut/O already uses G. Please correct the
design constraints accordingly.

I'm sure I'm doing something really dumb here... but will using BEL
help fix this? Oh, and I'm using WebPack, so I dont have FPGA Editor.
Thank you.
-Jim

Hi Jim,

There is a connectivity problem that can be easily corrected. The SRL16
needs to be in the G-LUT. Since the connection from the G-LUT to the
MUXF5 uses the I0 input in the hardware, your code needs to do the same,
but you have the SRL16 driving the I1 input of the MUXF5. The code works
okay if I swap the MUXF5 inputs to match the hardware:

the_muxf5: MUXF5
port map (
i0 => internal_2,
i1 => internal_1,
o => y,
s => sel
);

Number of occupied Slices: 1 out of 256 1%

Regards,
Bret

Jim George
Guest

Posted: Tue Dec 14, 2004 1:14 am Post subject: Re: LUT and MUXF5 placement

Quote:

Thanks, it works fine now!

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