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http://www.theregister.co.uk/2005/02/01/cell_analysis_part_one/
The Cell chip - what it is, and why you should care
By Andrew Orlowski in San Francisco
Published Tuesday 1st February 2005 22:07 GMT
Analysis No chip in years has caused as much excitement as the Cell
processor developed by IBM, Sony and Toshiba. It promises to be the most
important microprocessor of the decade, with potentially enormous
repercussions for how the industry computes, and how the rest of us use
digital media. It will power the PlayStation 3 and technical and commercial
computing.

Technical details of Cell will be disclosed at the International Solid State
Circuits Conference in San Francisco next week, and in anticipation we'll
look first at how the Cell works and then tomorrow at what it means to the
industry and consumers.

Excitement about Cell has already led to some wild and poorly informed
speculation, as Ars Technica's Jon Stokes rued last week. But earlier in the
month, Microprocessor Report's Tom Halfhill published an investigation into
a detailed patent filed in 2001, and published by the USPTO in October, and
he was kind enough to discuss it with us. We'll refer to it as the '734
patent.
Inside Cell
The ambitious scale of the project is one of the most remarkable aspects of
Cell.

"It isn't just a single microprocessor or even a family of processors,"
writes Tom. "It's a top-to-bottom architecture for a broad range of
computing systems, from servers and workstations at the high-end to game
consoles, PDAs, digital TVs, and other consumer electronics at the low end".

How does it look?

The 'cell' which gives the chip its name doesn't refer to the hardware, but
to a virtual clump of software which roams the system looking for computing
resources. The patent refers to a "cell object" - program and data - and it
can even roam across LANs or WANs, to find another Cell-based device.

A Cell chip consists of one or more independent execution units, and a
program can commandeer as many of these as resources allow to create a
temporary execution pipeline, each with its own register file and banks of
RAM. These pipelines are dynamically configurable and can lock out other
processes from grabbing their hardware resources. "The Cell architecture
introduces a whole new meaning to the term 'self-modifying code'," notes Tom
drily.

The '734 patent calls the basic hardware unit a PE, or 'processor element'.
Rather confusingly, a PE consists of a 'processor unit' or PU, and an array
of attached, er, processing units or APUs. The patent, Tom notes, says that
the "preferred" PE configuration is eight APUs. The "preferred embodiment"
of an APU is 128kb of SRAM, 128 x 128-bit registers, four integer units and
four floating point units. Some of these may be specialized for tasks such
as shading.

Inside each software cell are 'apulets'. These aren't necessarily
self-contained programs, stress MPR, but seem more like serialized objects.
Amongst the many mysteries yet to be revealed about software cells is how
the chip schedules such tasks, not just amongst onboard PEs but also amongst
other Cells.

"Imagine an apulet running on your PDA that depends on a result coming from
another apulet running on a computer in Norway," writes Tom. The Cell
processor must make its best guess, based on network latencies, how to
distribute the workload. The designers have set themselves an awesome
challenge.

Halfhill also notes that the Cell's architecture is more flexible than
Java's sandboxes, because a software cell can encapsulate several processes,
or part of a single process. There's no evidence, he points out, that Cell
implements JVMs in hardware: it's much more subtle than that. For security
purposes, Cell's hardware restrictions may prove to be the most
controversial aspect of the chip.

Some interesting design decisions have been made in creating the memory
architecture -

"It's hard to avoid the conclusion that Cell processors will have an
extraordinarily secure but cumbersome memory model. For each main-memory
access, the processor would have to consult four lookup tables... Three of
those tables are in DRAM, which implies slow off-chip memory references; the
other table is in the DMA controller's SRAM. In some cases, the delays
caused by the table lookups might eat more clock cycles than reading or
writing the actual data. The patent hints that some keys might unlock
multiple memory locations or sandboxes, perhaps granting blanket permission
for a rapid series of accesses, within certain bounds."

Global security
The Cell architecture isn't just a blueprint for a new kind of chip, but for
a massively distributed global computing network. Each Cell is given a GUID,
a global identifier. Your PlayStation may be hosting processes that began
life on a Cell on another side of the world. Remember that the architecture
enables a strict, lock-down machine to be built, with access to memory
tightly controlled. Since DRM is predicated on controlling
uniquely-identified media to run, or not run, on a specifically-authorized
piece of hardware, this allows system designers much more scope in building
systems which can both restrict and track the content they play.

There may be more benign uses: Cell clearly makes a very sophisticated
building block for distributed grid computing too. "A hypothetical Cell
processor with eight of these APUs could achieve 32 BOPS and 32 gigaFLOPS at
only 250MHz," writes Tom. Or a teraflop at 1Ghz. This is an order of
magnitude higher than today's workstations in what could be a low cost, low
power machine. If Cell fulfills its promise, Intel is facing its greatest
challenge since the turn of the 1990s, when RISC processors seemed to be
extending an unbeatable performance lead, and when Microsoft was porting
Windows NT to every RISC platform it could: MIPS, Alpha and PowerPC. But the
remarkable P6 core (which first appeared in the Pentium II) saw the
performance gap narrow, and the alliances arrayed against Intel stumbled and
fragmented.

This time, Cell is aimed at a different market, one that Wintel has failed
to conquer - the living room. ®

Ketil Malde · Guest

For those of you who are too lazy to read all this very interesting
and informative article, here's the executive summary:

Cell is simplay an amalgam of existing, vastly successful
technologies: IA-64-like Java chips running the equivalent of
ActiveX components.

:-)

-kzm
--
If I haven't seen further, it is by standing in the footprints of giants

Andrew Ryan Chang · Guest

NEXT BOX <nextbox@xbox2.net> wrote:

Alex Johnson · Guest

NEXT BOX wrote:

NEXT BOX · Guest

"Alex Johnson" <compuwiz@jhu.edu> wrote in message
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Jan Lucas · Guest

NEXT BOX schrieb:

Jacob Oost · Guest

Ketil Malde wrote:

NEXT BOX · Guest

I don't want to hype today *too* much, for fear of disappointment. but in
less than 10 hours, there is *supposed* to be quiet a bit of information
released on the Cell Processor Element, Cell APU and Cell PU. the basic
building blocks of Cell Processors and Cell Systems. As well as information
on the software side, if i'm not mistaken.

geeks have been waiting 4 years for this, since Cell was announced in early
2001.

Ken Hagan · Guest

NEXT BOX wrote:

Ryan · Guest

"NEXT BOX" <nextbox@xbox2.net> wrote in message
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Keith R. Williams · Guest

In article <36pufiF51ru0tU1@individual.net>, Ryan@aol.com says...

NEXT BOX · Guest

IBM, Sony, Sony Computer Entertainment Inc. and Toshiba Disclose Key
Details of the Cell Chip
Monday February 7, 1:00 pm ET
Innovative Design Features Eight Synergistic Cores Together with Power Based
Core, Delivers More Than 10 Times the Performance of the Latest PC
Processors

SAN FRANCISCO--(BUSINESS WIRE)--Feb. 7, 2005-- At the International Solid
State Circuits Conference (ISSCC) today, IBM, Sony Corporation, Sony
Computer Entertainment Inc. (Sony and Sony Computer Entertainment
collectively referred to as Sony Group) and Toshiba Corporation (Toshiba)
for the first time disclosed in detail the breakthrough multi-core
architectural design - featuring supercomputer-like floating point
performance with observed clock speeds greater than 4 GHz - of their jointly
developed microprocessor code-named Cell.

Source: IBM

· View multimedia news release

A team of IBM, Sony Group and Toshiba engineers has collaborated on
development of the Cell microprocessor at a joint design center established
in Austin, Texas, since March 2001. The prototype chip is 221 mm(2),
integrates 234 million transistors, and is fabricated with 90 nanometer SOI
technology.

Cell's breakthrough multi-core architecture and ultra high-speed
communications capabilities deliver vastly improved, real-time response for
entertainment and rich media applications, in many cases 10 times the
performance of the latest PC processors.

Effectively a "supercomputer on a chip" incorporating advanced
multi-processing technologies used in IBM's sophisticated servers, Sony
Group's computer entertainment systems and Toshiba's advanced semiconductor
technology, Cell will become the broadband processor used for industrial
applications to the new digital home.

Another advantage of Cell is to support multiple operating systems, such as
conventional operating systems (including Linux), real-time operating
systems for computer entertainment and consumer electronics applications as
well as guest operating systems for specific applications, simultaneously.

Initial production of Cell microprocessors is expected to begin at IBM's
300mm wafer fabrication facility in East Fishkill, N.Y., followed by Sony
Group's Nagasaki Fab, this year. IBM, Sony Group and Toshiba expect to
promote Cell-based products including a broad range of industry-wide
applications, from digital televisions to home servers to supercomputers.

Among the highlights of Cell released today:

* Cell is a breakthrough architectural design -- featuring eight synergistic
processors and top clock speeds of greater than 4 GHz (as measured during
initial hardware testing)
* Cell is a multicore chip capable of massive floating point processing
* Cell is OS neutral and supports multiple operating systems simultaneously

"Today's disclosure of the Cell chip's breakthrough architectural design is
a significant milestone in an ambitious project that began four years ago
with the creation of the IBM, Sony and Toshiba design lab in Austin, Texas,"
said William Zeitler, senior vice president and group executive, IBM Systems
and Technology Group. "Today we see the tangible results of our
collaboration: an open, multi-core, microprocessor that portends a new era
in graphics and multi-media performance."

"Today, we are very proud to share with you the first development of the
Cell project, initiated with aspirations by the joint team of IBM, Sony
Group and Toshiba in March 2001," said Ken Kutaragi, executive deputy
president and COO, Sony Corporation, and president and Group CEO, Sony
Computer Entertainment Inc. "With Cell opening a doorway, a new chapter in
computer science is about to begin."

"We are proud that Cell, a revolutionary microprocessor with a brand new
architecture that leapfrogs the performance of existing processors, has been
created through a perfect synergy of IBM, Sony Group and Toshiba's
capabilities and talented resources, "said Masashi Muromachi, corporate vice
president of Toshiba Corporation and president & CEO of Toshiba's
Semiconductor Company. "We are confident that Cell will provide major
momentum for the progress of digital convergence, as a core device
sustaining a whole spectrum of advanced information-rich broadband
applications, from consumer electronics, home entertainment through various
industrial systems."

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http://biz.yahoo.com/bw/050207/75391_1.html
Cell Processor Uses Rambus High Speed Interface Solutions
Monday February 7, 1:01 pm ET
XDR(R) DRAM and Redwood FlexIO(TM) Processor Bus Provide Unprecedented
Bandwidth for Next-Generation Computer and Consumer Applications

SAN FRANCISCO--(BUSINESS WIRE)--Feb. 7, 2005-- Rambus Inc. (Nasdaq:RMBS -
News), a leading developer of chip interface products and services, today
revealed that the Cell processor incorporates Rambus's XDR memory and
FlexIO(TM) processor bus interface solutions. Cell is the highly-anticipated
advanced microprocessor developed by Sony Corporation, Sony Computer
Entertainment, Toshiba Corporation and IBM. The memory and processor bus
interfaces designed by Rambus account for 90% of the Cell processor signal
pins, providing an unprecedented aggregate processor I/O bandwidth of
approximately 100 gigabytes-per-second.
Rambus is scheduled to discuss the Cell interface clocking and circuit
design at the International Solid State Circuits Society conference in San
Francisco on February 9, 2005.

"The Cell processor, that has overwhelming computational power, demands
another overwhelming data transfer capability between Cell and main memory
system, and Input/Output systems. Rambus, underpinned by its expertise in
latest memory technology, provided us with a clear solution that was
absolutely the best match to Cell," said Ken Kutaragi, executive deputy
president and COO, Sony Corporation, and president and Group CEO, Sony
Computer Entertainment Inc. "I respect Rambus and all our team members that
collaborated together for completing this challenging work with all the
technology and enthusiasm they possess."

"We have been busy working with the Sony Group and Toshiba on the
development of the Cell processor for the past couple of years and we're
excited to see this advanced engineering effort become a reality," said
Harold Hughes, chief executive officer at Rambus. "Our engineering teams
have not only designed and developed the world's fastest memory and logic
interfaces but we continue to help our customers integrate various system
components which enable them to bring high-performance, high-value products
to the market."

The Rambus XDR memory interface, capable of data rates of 3.2GHz to 8.0GHz,
achieves data rate speeds that are an order of magnitude higher than today's
mainstream PC memory systems while utilizing fewer DRAMs and fewer
controller pins. FlexIO processor buses, formerly codenamed Redwood, are
capable of running up to 6.4GHz data rates providing bandwidth more than
four times faster than best-of-class processor buses available today. All
Rambus high-speed interfaces are developed as complete solutions for
high-volume, low-cost systems.

Sony and Toshiba signed a licensing agreement with Rambus in January 2003.
Since then the engineering teams have worked closely to design and develop
the high-bandwidth interface solutions necessary for next-generation
computing and consumer devices.

About Rambus Inc.

Rambus is one of the world's leading providers of advanced chip interface
products and services. Since its founding in 1990, the company's
innovations, breakthrough technologies and integration expertise have helped
industry-leading chip and system companies solve their most challenging and
complex I/O problems and bring their products to market. Rambus's interface
solutions can be found in numerous computing, consumer, and communications
products and applications. Rambus is headquartered in Los Altos, California,
with regional offices in Chapel Hill, North Carolina, Taipei, Taiwan and
Tokyo, Japan. Additional information is available at www.rambus.com.

Note to Editors: For information on the Cell processor, please see "IBM,
Sony, Sony Computer Entertainment Inc. and Toshiba Disclose Key Details of
the Cell Chip" press release issued today at 10:00 a.m. PST.

Ar Q · Guest

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