| Author |
Message |
Jack
Guest
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 Posted:
Thu Feb 17, 2005 7:56 am Post subject:
interconnection in embedded multiprocessors |
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hi
When embedding multiprocessors with a mesh interconnection in NUMA
scheme, we have some basic problems.
Consider each processor has its local memory (most probably with the
local bus), I need to make mesh interconnection. Then questions are
- Should we use point-to-point links between processors (register file
to register file)? This scheme looks more message passing machine. Can
we realize NUMA machine with this scheme ?
- Or should we use bus based interconnection (I guess this is correct)?
Suppose we have to use the bus based interconnection, we need a special
memory controller and bus arbitrator, in order for one of each
processor access remote memory exclusively (i hope this is correct).
Then
- What is the efficient (well-known) scheme to solve memory / bus
conflict problem ?
I am a newbie in this issue and someone could provide a hint-comment or
link or reading materials...
thanks |
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Del Cecchi
Guest
|
| Posted:
Thu Feb 17, 2005 7:12 pm Post subject:
Re: interconnection in embedded multiprocessors |
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Jack wrote:
| Quote: | hi
When embedding multiprocessors with a mesh interconnection in NUMA
scheme, we have some basic problems.
Consider each processor has its local memory (most probably with the
local bus), I need to make mesh interconnection. Then questions are
- Should we use point-to-point links between processors (register file
to register file)? This scheme looks more message passing machine. Can
we realize NUMA machine with this scheme ?
|
You can realize numa with any scheme. I don't get the register file to
register file bit though.
| Quote: |
- Or should we use bus based interconnection (I guess this is correct)?
|
You can use bus also. That will make it really really numa.
| Quote: |
Suppose we have to use the bus based interconnection, we need a special
memory controller and bus arbitrator, in order for one of each
processor access remote memory exclusively (i hope this is correct).
Then
- What is the efficient (well-known) scheme to solve memory / bus
conflict problem ?
|
An arbitrator arbitrates. Unless it is the NHL. So use locks and a
round robin arbitration scheme.
| Quote: |
I am a newbie in this issue and someone could provide a hint-comment or
link or reading materials...
thanks
|
This seems a little involved for a newbie.
del |
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Jack
Guest
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| Posted:
Fri Feb 18, 2005 3:04 pm Post subject:
Re: interconnection in embedded multiprocessors |
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Hi
Actually it comes to me unclear. In case we use bus based
interconnection of 4 processor MESH, Does it mean there are 4 buses?
Is it your meaning that round robin arbitration is for bus, lock is
for memory ?
Actually bus arbiter is available as an IP and what about 'lock' IP
(for example, for FPGA )? |
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Jack
Guest
|
| Posted:
Fri Feb 18, 2005 6:06 pm Post subject:
Re: interconnection in embedded multiprocessors |
|
|
Hi
Actually it comes to me unclear. In case we use bus based
interconnection of 4 processor MESH, Does it mean there are 4 buses?
Is it your meaning that a round robin arbitration is for bus, 'lock'
is
for memory ?
Actually bus arbiter is available as an IP and what about 'lock' IP
(for example, for FPGA )?
In case one processor want to acess the remote memory using a shared
variable, then we need a routing hardware....
Memories may need 4 bidirectional ports, we need a address decoder as
well.
So could someone also suggest efficient routing sheme and address
decoding scheme?
Reading material on this bus based (on chip) DSM will be of thank.
thankyou for help for newbie |
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Guest
|
| Posted:
Wed Feb 23, 2005 7:56 am Post subject:
Re: interconnection in embedded multiprocessors |
|
|
Jack wrote:
| Quote: | Hi
Actually it comes to me unclear. In case we use bus based
interconnection of 4 processor MESH, Does it mean there are 4 buses?
Is it your meaning that a round robin arbitration is for bus, 'lock'
is
for memory ?
Actually bus arbiter is available as an IP and what about 'lock' IP
(for example, for FPGA )?
In case one processor want to acess the remote memory using a shared
variable, then we need a routing hardware....
Memories may need 4 bidirectional ports, we need a address decoder as
well.
So could someone also suggest efficient routing sheme and address
decoding scheme?
Reading material on this bus based (on chip) DSM will be of thank.
thankyou for help for newbie
|
Maybe this is too simple for you, however,
You may wish to consider Chuck Moore's 25X ( multicomputer)
as a /ultra high efficiency/ router/decoder
scheme? ( hint, use a maximum of 5 processes
for position dependent multiplexing )
maw |
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