megha_rao
Joined: 17 Feb 2005
Posts: 2
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 Posted:
Thu Feb 17, 2005 7:06 pm Post subject:
Master's project |
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I am a graduate student studying at California State University, Sacramento.I am pursuing my MS in EEE specialized in CMOS/ VLSi. I have taken up some courses in Verilog and Microcomputer System Design. I am looking forward to start my Master's project in Digital Systems using Verilog but am finding it difficult to finalize on a topic; I really don't understand where to start. I was wondering if anyone could help me out with some ideas; I would be really grateful.
Thanking You.
Sincerely,
Megha. |
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absk
Guest
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Sat Feb 19, 2005 2:50 am Post subject:
Re: Master's project |
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Do you have to implement something in verilog or make something novel
towards a thesis?
In case you just want to implement something existing, maybe you can
design a 32-bit pipelined microprocessor and to make things complex,
you can also incorporate branch prediction schemes and some other
features as in current microprocessors depending on how much complex
you want to make it.
If you want to do something novel, then your thesis advisor should be
the best person for this.
Abhishek
megha_rao wrote:
| Quote: | I am a graduate student studying at California State University,
Sacramento.I am pursuing my MS in EEE specialized in CMOS/ VLSi. I
have taken up some courses in Verilog and Microcomputer System
Design. I am looking forward to start my Master's project in Digital
Systems using Verilog but am finding it difficult to finalize on a
topic; I really don't understand where to start. I was wondering if
anyone could help me out with some ideas; I would be really
grateful.
Thanking You.
Sincerely,
Megha. |
|
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