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Guest
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 Posted:
Sat Feb 19, 2005 2:13 pm Post subject:
shared memory programming on distributed memory model? |
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hi
I implemented multiprocessors in distributed local memory manner on
FPGA. Processors are point to point communicate, purely in a message
passing. And I find the programming is very architecture dependent and
laborous. So I am looking for the method of the realizing the shared
memory abstraction on physically distributed memory machine. Any remark
or document pointing will be appreciated. |
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del cecchi
Guest
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| Posted:
Sun Feb 20, 2005 7:55 am Post subject:
Re: shared memory programming on distributed memory model? |
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<jaeyoung_hur@yahoo.com> wrote in message
news:1108804436.013859.291510@o13g2000cwo.googlegroups.com...
| Quote: | hi
I implemented multiprocessors in distributed local memory manner on
FPGA. Processors are point to point communicate, purely in a message
passing. And I find the programming is very architecture dependent and
laborous. So I am looking for the method of the realizing the shared
memory abstraction on physically distributed memory machine. Any
remark
or document pointing will be appreciated.
If you want to avoid the evils of message passing, then ccNUMA is for |
you. A number of companies manufacture them. The earliest papers I
recall reading were DASH from Stanford. See also SCI, IEEE1596
standard. SGI origin systems are ccNUMA, as are some X series from IBM,
Superdome from HPQ. I believe DASH was followed by FLASH, also at
Stanford. I'm sure the manufacturers have white papers or other stuff
about their NUMA systems.
A little google and some luck should get you going.
del |
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Guest
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| Posted:
Sun Feb 20, 2005 10:16 pm Post subject:
Re: shared memory programming on distributed memory model? |
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del cecchi wrote:
| Quote: | If you want to avoid the evils of message passing, then ccNUMA is for
you. A number of companies manufacture them. The earliest papers I
recall reading were DASH from Stanford. See also SCI, IEEE1596
standard. SGI origin systems are ccNUMA, as are some X series from
IBM,
Superdome from HPQ. I believe DASH was followed by FLASH, also at
Stanford. I'm sure the manufacturers have white papers or other
stuff
about their NUMA systems.
A little google and some luck should get you going.
|
three SCI were convex exemplar (hp processors), sequent (intel
processors), and DG (intel processors). HP bought convex. IBM bought
Sequent, and DG (?, their disk arrays sold off and somebody bought
their brand new campus complex)
at least convex and sequent did a fair amount on partitioning and
locality ... sort of an intermediate stage akin to cache locality and
cache miss rates. convex heavily modified MACH; sequent modified their
dynix system.
SCI was oriented towards taking syncronous bus protocols and converting
them to dual-simplex asyncronous (hardware) message(?) protocol.
Standard SCI memory "bus" has 64-ports; convex put dual HP processor
boards at each "port" (128 processors). Sequent and DG put quad Intel
processor boards at each "port" (256 processors).
SCI has been applied to stuff other than memory bus.
i found it interesting in late '80s & early 90s period .... LANL was
driving COTS factor for cray channel in standards meetings (HiPPI),
LLNL was pushing COTS for what became fiber-channel standard, and SLAC
was the driving force behind COTS for SCI. |
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