Jerome
Guest
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 Posted:
Thu Dec 09, 2004 4:09 pm Post subject:
Multi-Sharc architecture |
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After discussing with ADI support, the part 21367 seems to better
match our requirements :
- Supports multiprocessing and its on-chip bus arbitration logic
allows glueless connection of up to 4 DSPs
- 2400 MFLOPS instead of 1200 for the 21262
- in addition it features a SDRAM controller that could be useful to
design a generic audio platform.
- 8 SPORTS instead of 6 for the 21262
My questions ...
Is this multi-processor function managed by the pins memory select
MS0-3, does this means the built-in multiprocessing feature is based
on external
shared memory only, since the 21367 doesnt feature any link port ?
In the case of we would like to use 4 banks of external SDRAM to store
audio
samples for instance, it seems these memory select pins are
multiplexed for accessing to extrenal SDRAM banks, as well as for
multi processor external memory bus arbitration, am I wrong ?
I mean can we use the multiprocessing feature of the 21367 if we use 4
banks
of SDRAM to store audio samples ?
thanks to all
jerome |
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Jon Harris
Guest
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| Posted:
Thu Dec 09, 2004 11:42 pm Post subject:
Re: Multi-Sharc architecture |
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I only have experience with the older SHARCs (21065L, 21161N). But here is how
they work:
Multiprocessor support means that each processor can read/write the internal
memory of the other SHARCs using the shared address/data bus. Sometimes the
whole memory space is not available, only a portion of it. They have bus
request (BR1, BR2, etc.) pins that they assert to request access to the shared
data/address bus.
They can also share a single SDRAM by arbitrating for who wants/gets access to
it at a given time.
Assuming it is the same for the 21367, you should still be able to use both
shared SDRAM and the multiprocessing features.
When you say 4 banks of external SDRAM, are you talking about 4 separate chips?
This is a little confusing to me since a single SDRAM chip often contains more
than one bank (usually 2 or 4). For example, Micron has a chip that is 1 Meg x
32 x 4 banks (MT48LC4M32B2).
"Jerome" <email.trash@caramail.com> wrote in message
news:64c78a71.0412090309.6fc58618@posting.google.com...
| Quote: | After discussing with ADI support, the part 21367 seems to better
match our requirements :
- Supports multiprocessing and its on-chip bus arbitration logic
allows glueless connection of up to 4 DSPs
- 2400 MFLOPS instead of 1200 for the 21262
- in addition it features a SDRAM controller that could be useful to
design a generic audio platform.
- 8 SPORTS instead of 6 for the 21262
My questions ...
Is this multi-processor function managed by the pins memory select
MS0-3, does this means the built-in multiprocessing feature is based
on external
shared memory only, since the 21367 doesnt feature any link port ?
In the case of we would like to use 4 banks of external SDRAM to store
audio
samples for instance, it seems these memory select pins are
multiplexed for accessing to extrenal SDRAM banks, as well as for
multi processor external memory bus arbitration, am I wrong ?
I mean can we use the multiprocessing feature of the 21367 if we use 4
banks
of SDRAM to store audio samples ?
thanks to all
jerome |
|
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