| Author |
Message |
Jim Brain
Guest
|
 Posted:
Tue Dec 14, 2004 9:58 am Post subject:
Need help with CUPL |
|
|
I have tried reading up on CUPL for a CPLD project, but I have been less
than successful. Is there a good tutorial on some of the advanced CUPL
stuff?
In my case, I have some combinatorial logic (CE_OUT=CE_IN & !A7 & !A6 &
!A5 & !A4 & !A3), and I grok that pretty well.
But, in my design, I need to implement a read/write register, and I
can't find a good example in CUPL to implement it. The Data lines need
to be HiZ unless the register is being accessed, and if it is, lines go
to latch input if Write, lines go to latch output if read.
Examples would be fine, or just links to a good tutorial that would show
a register would be perfect.
Jim
--
Jim Brain, Brain Innovations
brain@jbrain.com http://www.jbrain.com
Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times! |
|
| Back to top |
|
 |
Andreas Hölscher
Guest
|
| Posted:
Tue Dec 14, 2004 11:45 am Post subject:
Re: Need help with CUPL |
|
|
Jim Brain wrote:
| Quote: | I have tried reading up on CUPL for a CPLD project, but I have been less
than successful. Is there a good tutorial on some of the advanced CUPL
stuff? |
I don't know a tutorial as I don't use CUPL any more
But, in my design, I need to implement a read/write register, and I
can't find a good example in CUPL to implement it. The Data lines need
to be HiZ unless the register is being accessed, and if it is, lines go
to latch input if Write, lines go to latch output if read.
a 4-bit register from an old CUPL-file build with D-FFs:
===========><============
pcadrio = [sa9..sa0];
" write:
[reset_ff,swapmem,vcion,reserve].clk = !((pcadrio==^h390) & !iow & !aen);
[reset_ff,swapmem,vcion,reserve].ar = resetdrv;
[reset_ff,swapmem,vcion,reserve].d = [pcd0, pcd1, pcd2, pcd3
].pin;
" read:
[pcd0, pcd1, pcd2, pcd3] = [reset_ff,swapmem,vcion,reserve];
[pcd0, pcd1, pcd2, pcd3].oe = (pcadrio==^h390)& !ior & !aen;
===========><============
another register build without FFs (just the "write" part of it):
===========><============
pullupw = !( (!cspullup & !write & !data.pin) # !reset
# !(!cspullup & !write & data.pin) & !pullupw);
===========><============
Hope it helps.
Andreas
--
DSA Daten- und Systemtechnik GmbH | mailto:ah@dsa-ac.de
Dipl.-Ing. Andreas Hölscher | http://www.dsa-ac.de
Pascalstr. 28 | Tel.: +49 2408 9492-645
D-52076 Aachen | Fax.: +49 2408 9492-92
Germany | PGP Key ID: 0x3EFCA3C6 |
|
| Back to top |
|
|
Pavel Semyonov
Guest
|
| Posted:
Tue Dec 14, 2004 8:22 pm Post subject:
Re: Need help with CUPL |
|
|
Jim,
We have been using CUPL for about 8 years ago. If you want, I can find you
one of our two old CUPL projects, whcih you can use a refernce. SHould you
wonna this, just email me.
--
Regards,
Pavel |
|
| Back to top |
|
|
Jim Granville
Guest
|
| Posted:
Wed Dec 15, 2004 1:23 am Post subject:
Re: Need help with CUPL |
|
|
Jim Brain wrote:
| Quote: | I have tried reading up on CUPL for a CPLD project, but I have been less
than successful. Is there a good tutorial on some of the advanced CUPL
stuff?
In my case, I have some combinatorial logic (CE_OUT=CE_IN & !A7 & !A6 &
!A5 & !A4 & !A3), and I grok that pretty well.
But, in my design, I need to implement a read/write register, and I
can't find a good example in CUPL to implement it. The Data lines need
to be HiZ unless the register is being accessed, and if it is, lines go
to latch input if Write, lines go to latch output if read.
Examples would be fine, or just links to a good tutorial that would show
a register would be perfect.
|
These for Atmel devices - this for a HC574 Octal D type device :
[DB7..DB0].oe = !RDN;
/* Enable on READ LOW => read back Latch contents */
[DB7..DB0].ck = WRN; /* Latch on the trailing edge of WRN ___/=== */
[DB7..DB0].d = [DB7..DB0].io; /* D feeds from BUS io pins */
Also, some Atmel devices support this: - equiv to a HC573 Latch device
[DB7..DB0].LE = !WRN; /* Latch transparent during WRN LOW */
[DB7..DB0].L = [DB7..DB0].io; /* D feeds from BUS io pins */
-jg |
|
| Back to top |
|
|
Jim Brain
Guest
|
| Posted:
Sat Dec 18, 2004 7:56 am Post subject:
Re: Need help with CUPL |
|
|
I appreciate the responses. I'll look at them to finish this.
One person emailed me asking why I am using CUPL. As I'm new to
programmable logic, I decided it'd be best to start with a CPLD. I
obtained 2 from Digikey, an ATF750 and a Atmel 1504AS. After delivery,
I went trolling for a piece of software to use to program them, thus
WinCUPL.
The email suggested ABEL, and I'll give that a shot as well. Another
person suggested I dload WebPack or Xilinx's offering, draw the
schematic, and export as a VHDL file, load into WinCUPL, and go from there.
I dloaded WebPack, drew my schematic (I'm a software developer, but I am
struggling with VHDL. Schematics, OTOH, I can draw very easily). I
managed to get the schematic to compile on Quartus (with warnings about
my inout pins being tied to VCC or something, so I suspect I've done
something wrong), so I exported as VHDL (looks nasty, like decompiled C
code), and imported into WinCUPL. No go.
Reading the newsgroup for a few weeks, I am obviously not in the same
league as most who frequent here, but it just seems very hard for a new
entrant to programmable logic to get a CPLD going. I'd love to go
straight to FPGAs, but the entire circuit is a 5 FF, 20 gate design, so
an FPGA and an EPROM seems overkill.
Am I going about this the wrong way? Should I avoid CUPL like the
plague? Is ABEL my best bet for CPLD design, or is there a reasonable
VHDL tool that will give me files I can program into a 750 or 1504, or
industry std PAL/GALs? I sense the VHDL versus Verilog discussion is
like the VI versus EMACS discussion, how does a newbie like me, decide
which to pick to learn first? Google didn;t turn up a FAQ for this
newsgroup, but I'd assume some of these questions would be in a FAQ...
The online helps are very targeted, but none seem to answer the above
questions.
As an outsider looking in, I've noticed the Altera/Xilinx discussion is
another pseudo-religious war, but I often see the voice of "reason"
suggest that people simply need to load their model into both design
tools, see who handles the model better, and choose designs based on
that information. I think that's wise advice, but it doesn't help
people like myself who know neither tool well, and are just starting
out. Newcomers, like myself, typically have small designs, low speed,
and need lots of help while using the tool initially. For that type of
user, is it possible for me to ask for recommendations without
triggering a war? I know not everyone's taste is the same, but right
now, best is defined to me as easiest to succeed at.
Jim, still trying to figure out how to tie into output enable on inout
pins on his schematic, Brain
--
Jim Brain, Brain Innovations
brain@jbrain.com http://www.jbrain.com
Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times! |
|
| Back to top |
|
|
Jim Granville
Guest
|
| Posted:
Sat Dec 18, 2004 3:35 pm Post subject:
Re: Need help with CUPL |
|
|
Jim Brain wrote:
| Quote: | I appreciate the responses. I'll look at them to finish this.
One person emailed me asking why I am using CUPL. As I'm new to
programmable logic, I decided it'd be best to start with a CPLD. I
obtained 2 from Digikey, an ATF750 and a Atmel 1504AS. After delivery,
I went trolling for a piece of software to use to program them, thus
WinCUPL.
The email suggested ABEL, and I'll give that a shot as well. Another
person suggested I dload WebPack or Xilinx's offering, draw the
schematic, and export as a VHDL file, load into WinCUPL, and go from there.
I dloaded WebPack, drew my schematic (I'm a software developer, but I am
struggling with VHDL. Schematics, OTOH, I can draw very easily). I
managed to get the schematic to compile on Quartus (with warnings about
my inout pins being tied to VCC or something, so I suspect I've done
something wrong), so I exported as VHDL (looks nasty, like decompiled C
code), and imported into WinCUPL. No go.
|
If you look at the REPORT files from Altera, or Xilinx tools, you will
see Boolean Eqn formats, and that is quite close to CUPL.
| Quote: |
Reading the newsgroup for a few weeks, I am obviously not in the same
league as most who frequent here, but it just seems very hard for a new
entrant to programmable logic to get a CPLD going. I'd love to go
straight to FPGAs, but the entire circuit is a 5 FF, 20 gate design, so
an FPGA and an EPROM seems overkill.
|
It is. A SPLD/CPLD is the best solution.
| Quote: |
Am I going about this the wrong way? Should I avoid CUPL like the
plague?
|
No, CUPL is pretty much the only currently supported flow for the
ATF750/SPLDs. ABEL is no longer generically available, since Xilinx took
over, but it (or a close variant) is still offered by some vendors.
| Quote: | Is ABEL my best bet for CPLD design, or is there a reasonable
VHDL tool that will give me files I can program into a 750 or 1504, or
industry std PAL/GALs?
|
VHDL has a much greater learning curve, than CUPL.
CUPL is simpler, ( rather like structured Assembler vs Java ), and
you use the DOT extensions [.CK, .D, .OE, .IO etc ) to 'create the
circuit' you would have drawn on paper.
You also KNOW exactly what PLD resoutce it will use, at the time
you write the code.
CUPL can also create test vectors that any good device programmer can
run after PGM, to verify the actual silicon operation.
These test vectors also allow you to verify and identify secured
devices - eg in a field return : Is the PLD still OK, and what version
is it ?
CUPL is a good fit for ATF16V8/ATF22V10/ATF750/ATF1502/ATF1504
SPLD/CPLD, but you would not design a soft-cpu using CUPL.
You could also look at ICT's PEEL SPLD/CPLD, and their WinPLACE.
I prefer the command line nature of CUPL, but you may like the
graphical nature of WinPLACE.
See http://www.anachip.com/eng/product/pld.php
-jg |
|
| Back to top |
|
|
Rich Webb
Guest
|
| Posted:
Sat Dec 18, 2004 7:23 pm Post subject:
Re: Need help with CUPL |
|
|
On Sat, 18 Dec 2004 06:05:07 GMT, Jim Brain <brain@jbrain.com> wrote:
| Quote: | I appreciate the responses. I'll look at them to finish this.
One person emailed me asking why I am using CUPL. As I'm new to
programmable logic, I decided it'd be best to start with a CPLD. I
obtained 2 from Digikey, an ATF750 and a Atmel 1504AS. After delivery,
I went trolling for a piece of software to use to program them, thus
WinCUPL.
|
As Jim G noted, CUPL (or the currently available and free (always nice)
WinCUPL) is a good fit for smaller PLDs. Devices like the 22V10 are
great for learning, being fairly inexpensive and are also available in
DIP form-factors with 5 V supplies -- handy to be able to "make
something" without having to spin a board for a TQFP footprint.
When you start reaching beyond SPLD-land, you probably should bite the
bullet and learn VLDH or Verilog. Take a look at both. If you're already
comfortable in C then Verilog may feel more comfortable to start with.
Once you know either, though, learning the other isn't too bad.
--
Rich Webb Norfolk, VA |
|
| Back to top |
|
|
sam
Guest
|
| Posted:
Thu Dec 30, 2004 9:34 pm Post subject:
Re: Need help with CUPL |
|
|
| Quote: | Reading the newsgroup for a few weeks, I am obviously not in the same
league as most who frequent here, but it just seems very hard for a new
entrant to programmable logic to get a CPLD going. I'd love to go
straight to FPGAs, but the entire circuit is a 5 FF, 20 gate design, so
an FPGA and an EPROM seems overkill.
|
I can certainly relate.
In my case I bought a Altera Max 7000 ... along with the Devry Esoc
board (Thank God for Ebay) then realized they were OVERKILL for what
I wanted to do (simple state machines, and decode/glue logic) so I
purchased a bunch of reprogrammable 22v10's (amd palce') and BPmicro's
PLD-1128.
I have been using them since and learning a lot, and my goal of designing
a 6502 based SBC (that I FULLY understand) edges closer and closer to
fruition.
The fun aspect of this approach is that once I go OUTSIDE the PLD I am
forced to revisit my old books on dc/ac analysis,circuit theory etc. (Its
an interesting perspective for someone with a Software Background).
| Quote: | Am I going about this the wrong way? Should I avoid CUPL like the
plague? Is ABEL my best bet for CPLD design, or is there a reasonable
VHDL tool that will give me files I can program into a 750 or 1504, or
industry std PAL/GALs?
|
Personally I chose to avoid VHDL because I felt CUPL would give me a
better understanding of what is going on AT THAT level. I can "see"
what I am doing ... when I am writing/simplifying the logic equation.
Besides the book I used began with CUPL and its focus was on the PAL/PLA
of yesteryear.
Do you have a choice with CPLD's? I dont know any CPLD's supported by
CUPL. |
|
| Back to top |
|
|
Rich Webb
Guest
|
| Posted:
Thu Dec 30, 2004 11:25 pm Post subject:
Re: Need help with CUPL |
|
|
| Quote: | Do you have a choice with CPLD's? I dont know any CPLD's supported by
CUPL.
|
Atmel's ATF15xx-series are supported by their free version of WinCUPL.
Not huge devices but, like the more common 22V10s, they do fill a niche
with 32 to 128 macrocells.
There's a "ATF15XX-DK2 CPLD Development/Programmer Kit" available from
Digikey, Arrow, etc. that includes an ISP cable, CUPL, and a 30-day
trial of their HDL compiler.
--
Rich Webb Norfolk, VA |
|
| Back to top |
|
|
Prototham
Joined: 06 Jul 2006
Posts: 1
Location: Woodbine Maryland
|
| Posted:
Thu Jul 06, 2006 5:42 pm Post subject:
Late but may help someone |
|
|
This is some CUPL code I use to do what you want. This is an 8 bit register that I can read and write to with a CPU.
/** pins declaration **/
pin = A1 ; /* address bus 1 */
pin = A2 ; /* address bus 2 */
pin = P1 ; /* IO */
pin = P2 ;
pin = P3 ;
pin = P4 ;
pin = P5 ;
pin = P6 ;
pin = P7 ;
pin = P8 ;
pin = d1 ; /* Databus IO */
pin = d2 ; /* */
pin = d3 ; /* */
pin = d4 ; /* */
pin = d5 ; /* */
pin = d6 ; /* */
pin = d7 ; /* */
pin = d8 ; /* */
pin = CS ; /* Chip Select 1 */
pin = RW ; /* Read /Write */
pinnode = W1 ;
pinnode = R1 ;
/** Logic Equations **/
W1 = !CS & !A1 & !A2 & !RW ;
R1 = !CS & !A1 & !A2 & RW ;
d1.oe = R1 ;
d2.oe = R1 ;
d3.oe = R1 ;
d4.oe = R1 ;
d5.oe = R1 ;
d6.oe = R1 ;
d7.oe = R1 ;
d8.oe = R1 ;
d1 = P1.io ;
d2 = P2.io ;
d3 = P3.io ;
d4 = P4.io ;
d5 = P5.io ;
d6 = P6.io ;
d7 = P7.io ;
d8 = P8.io ;
P1.D = d1 ;
P1.CK = W1 ;
P2.D = d2 ;
P2.CK = W1 ;
P3.d = d3 ;
P3.ck = W1 ;
P4.d = d4 ;
P4.ck = W1 ;
P5.d = d5 ;
P5.ck = W1 ;
P6.d = d6 ;
P6.ck = W1 ;
P7.d = d7 ;
P7.ck = W1 ;
P8.d = d8 ;
P8.ck = W1 ; |
|
| Back to top |
|
|
|
|
|
|
FAQ
Memberlist
Register
Profile
Log in to check your private messages
Log in
