| Author |
Message |
Sean Durkin
Guest
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 Posted:
Tue Dec 14, 2004 6:44 pm Post subject:
Linking FPGAs with RocketIOs |
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Hi *,
I'd like to establish a high-speed connection between two
Virtex-II-Pro-FPGAs, using several bidirectional
3,125Gbit/s-RocketIO-links in parallel (using e.g. Aurora). How do I
route something like this properly?
If I want to connect 2 FPGAs that are directly adjacent to each other,
the TX-pads are always opposite other TX-pads, and RX-pads always
opposite other RX-pads. So the way I see it I'd have to cross each and
every TX/RX-pair, like it's usually done in a cross-over-cable...
This makes vias in the signal path unavoidable, something I'd rather not
do if it can be avoided somehow. Any tips or tricks for this?
cu,
Sean |
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Symon
Guest
|
| Posted:
Tue Dec 14, 2004 9:41 pm Post subject:
Re: Linking FPGAs with RocketIOs |
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Sean,
Rotate one of the FPGAs by 180 degrees.
Symsx.
"Sean Durkin" <smd@despammed.com> wrote in message
news:41beee41$1@news.fhg.de...
| Quote: | Hi *,
I'd like to establish a high-speed connection between two
Virtex-II-Pro-FPGAs, using several bidirectional
3,125Gbit/s-RocketIO-links in parallel (using e.g. Aurora). How do I route
something like this properly?
If I want to connect 2 FPGAs that are directly adjacent to each other, the
TX-pads are always opposite other TX-pads, and RX-pads always opposite
other RX-pads. So the way I see it I'd have to cross each and every
TX/RX-pair, like it's usually done in a cross-over-cable...
This makes vias in the signal path unavoidable, something I'd rather not
do if it can be avoided somehow. Any tips or tricks for this?
cu,
Sean |
|
|
| Back to top |
|
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Petter Gustad
Guest
|
| Posted:
Wed Dec 15, 2004 1:17 am Post subject:
Re: Linking FPGAs with RocketIOs |
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|
Sean Durkin <smd@despammed.com> writes:
| Quote: | This makes vias in the signal path unavoidable, something I'd rather
not do if it can be avoided somehow. Any tips or tricks for this?
|
Swap the differential pairs and to polarity inversion on the receiver.
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail? |
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Sean Durkin
Guest
|
| Posted:
Wed Dec 15, 2004 12:13 pm Post subject:
Re: Linking FPGAs with RocketIOs |
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|
Symon wrote:
| Quote: | Sean,
Rotate one of the FPGAs by 180 degrees.
Won't help, the TX/RX positions are exactly the same on top and bottom |
side. If I rotate one FPGA, I again have TX-pairs opposite of other
TX-pairs, so to get to the RX-pair I have to cross signals again, same
thing...
cu,
Sean |
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Sean Durkin
Guest
|
| Posted:
Wed Dec 15, 2004 12:24 pm Post subject:
Re: Linking FPGAs with RocketIOs |
|
|
Sean Durkin wrote:
| Quote: | Symon wrote:
Sean,
Rotate one of the FPGAs by 180 degrees.
Won't help, the TX/RX positions are exactly the same on top and bottom
side. If I rotate one FPGA, I again have TX-pairs opposite of other
TX-pairs, so to get to the RX-pair I have to cross signals again, same
thing...
I take back everything I said and confess my stupidity to this |
newsgroup... have you ever had one of those days...? :)
Of course Symon was right...
cu,
Sean |
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Marc Randolph
Guest
|
| Posted:
Wed Dec 15, 2004 6:12 pm Post subject:
Re: Linking FPGAs with RocketIOs |
|
|
Petter Gustad wrote:
| Quote: | Sean Durkin <smd@despammed.com> writes:
This makes vias in the signal path unavoidable, something I'd
rather
not do if it can be avoided somehow. Any tips or tricks for this?
Swap the differential pairs and to polarity inversion on the
receiver. |
The p vs n trace order is just a matter of how you route out of the pin
field... I believe you can achieve either order at will.
I like Symon's idea of rotating one chip 180 degrees, but if the OP had
to keep them pointed the same direction for some crazy reason, he could
use the middle MGT for the TX and then one of the MGT's on either side
of it for RX, as needed. This only has to be done with one of the
devices - the other device can continue using a single MGT for both RX
and TX.
Hopefully the OP has a good clock reference and is using a fast speed
grade device... 3.125 Gbps is humming!
| Quote: | A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
|
Great sig!
Marc
--
http://www.getFirefox.com
10 million downloads in the past month. Do YOU have it? |
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John McCluskey
Guest
|
| Posted:
Wed Dec 15, 2004 6:26 pm Post subject:
Re: Linking FPGAs with RocketIOs |
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|
I think if you connect them head to head (top of device to top), then the
TX pads will face the RX pads. You can ignore the pair polarity, since
the receivers have a control bit to do polarity inversion.
John
On Tue, 14 Dec 2004 14:44:33 +0100, Sean Durkin wrote:
| Quote: | Hi *,
I'd like to establish a high-speed connection between two
Virtex-II-Pro-FPGAs, using several bidirectional
3,125Gbit/s-RocketIO-links in parallel (using e.g. Aurora). How do I
route something like this properly?
If I want to connect 2 FPGAs that are directly adjacent to each other,
the TX-pads are always opposite other TX-pads, and RX-pads always
opposite other RX-pads. So the way I see it I'd have to cross each and
every TX/RX-pair, like it's usually done in a cross-over-cable...
This makes vias in the signal path unavoidable, something I'd rather not
do if it can be avoided somehow. Any tips or tricks for this?
cu,
Sean |
|
|
| Back to top |
|
|
Sean Durkin
Guest
|
| Posted:
Wed Dec 15, 2004 6:50 pm Post subject:
Re: Linking FPGAs with RocketIOs |
|
|
Marc Randolph wrote:
| Quote: | I like Symon's idea of rotating one chip 180 degrees, but if the OP had
to keep them pointed the same direction for some crazy reason, he could
use the middle MGT for the TX and then one of the MGT's on either side
of it for RX, as needed. This only has to be done with one of the
devices - the other device can continue using a single MGT for both RX
and TX.
Problem is I need to use *ALL* MGTs, so that wouldn't work for me. But |
Symon's rotating-solution is perfect.
| Quote: | Hopefully the OP has a good clock reference and is using a fast speed
grade device... 3.125 Gbps is humming!
I'm using the Pletronics oscillator Xilinx recommends in the |
RocketIO-User-Guide. Speed-Grade is -6 and it's a device in a
flipchip-package, so at least according to the Xilinx-specs that should
be capable of 3.125Gbps.
cu,
Sean |
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