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GL · Guest

I'm using quartus 4.2, and create some fifo with the mega wizard.
on one side, synchronous data are writen at 27 MHz (from external
pins), and on the other side, I'm reading the data with a 80 MHz clock
(to my design).

The design assistant give me the following warnings :

Data bits are not synchronized when transferred between asynchronous
clock domains
Multiple data bits that are transferred across asynchronous clock
domains are synchronized, but not all bits may be aligned in receiving
clock domain

my fifos are :
- without common clock between read and write side
- the clocks are not synchronized
- in legacy synchronous mode
- perfomance are not maximized

What should I do ?

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Peter · Guest

GL, you have every right to expect your design to work.
Any FIFO worth its name must accomodate two unrelated clock domains,
one for reading, one for writing. That is actually quite trivial,using
a dual-port RAM for the data storage.
What is not so trivial is the reliable detection of FULL and EMPTY.
I work at Altera's competitor, but I do assume that Cyclone can handle
your requirements.
Otherwise: Welcome to the end of the alphabet...
I just tested our newest FIFO at roughly 500 and 200 MHz asynchronous
reads and writes, going EMPTY 200 million times a second, for a whole
week, with not a single decoding and control error.
So it can be done...
Peter Alfke, Xilinx Applications
========================
GL wrote:

Vaughn Betz · Guest

GL,

Your design sounds OK to me, but it's hard to be sure without seeing it.
Using FIFOs to transfer data between asynchronous clock domains is of course
standard usage, so the Quartus megawizard FIFOs will work fine for that.

I suspect we have an overzealous warning in the Design Assistant. The
warning you're getting is that when you transfer a data word (that is wider
than 1 bit), you have to be careful that all the bits arrive in the same
cycle in the receiving clock domain. A FIFO will take care of that.

If you send me your design, I'll open a software problem report on it, get
someone to check that the design analyzer isn't being too overcautious, and
if it is we'll fix this case.

Regards,

Vaughn Betz
Altera
v b e t z (at) altera.com [Remove spaces and add @ to reach me]

"GL" <a@b.c> wrote in message news:mn.753a7d4ca170b3de.23732@b.c...

Ben Twijnstra · Guest

Hi Peter,

Vaughn Betz · Guest

Hi GL,

I talked to one of our design experts, and he is almost certain he knows
what you're seeing (to be 100% sure he'd have to see the design, but he's
pretty confident he knows the issue).

The asynchronous FIFO has a path between two grey coded counters, with
appropriate metastability registers. The design assistant does not know
that the bank of registers involved in this transfer are grey-coded
counters, so it is flagging what appears to it to be a valid warning about a
multi-bit transfer across clock domains. The grey-coding makes this safe in
this case though, so you can ignore the warning.

There is already a software problem report open on this, and the long-term
solution is to make the design assistant aware of the higher-level
functionality of the FIFO.

If you want to make this warning go away, you can put a timing cut between
the two banks of registers (or between the two clock domains, but that is
more dangerous since it will cut all timing paths between the clock
domains). That will stop the design assistant from analyzing this transfer.

Regards,

Vaughn
Altera
v b e t z (at) altera.com [Remove spaces and add proper @ to reach me]

Peter · Guest

There was a designer named Gray
who spelled his name with an A
He showed us a trick
which counter to pick.
Thank heavens for dear Mr. Gray.

Happy Holidays!
Peter Alfke

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