| Author |
Message |
Craig Conway
Guest
|
 Posted:
Wed Dec 15, 2004 3:28 am Post subject:
Xilinx speed grading |
|
|
I'm trying to determine the delay curve of a particular path in a
Virtex2Pro -5 from min timing to max, including all points in between.
Obviously I can get the two end points (min and max) from the timing
analyzer, but I assume that points between the two don't necessarily fall on
a straight line. I considered also plotting the max timing of the other
speed grades (-7 and -6), but I don't know what their relationship to each
other is, so I wouldn't know exactly where to plot them relative to the -5
max endpoint.
If anyone knows where performance graphs might exist in the Xilinx
documenation, or what the relationship of speed grades to each other is, I'd
be most appreciative of a response.
Thanks! |
|
| Back to top |
|
 |
Peter
Guest
|
| Posted:
Wed Dec 15, 2004 4:40 am Post subject:
Re: Xilinx speed grading |
|
|
Craig, remember that "speed grades" are an artificial way of
segregating devices that are naturally made with a continuum of
performance parameters. To accomodate the unavoidable manufacturing
spread, IC manufacturers sort the devices into bins, so that they can
guarantee performance, but also sell the devices that came out slow or
"not so fast".
In a perfect world, all parameters would scale perfectly, i.e. a device
marked slow would have all its delays longer by the same factor, as
compared to the devices labeled fast.
The world is not perfect.
The only thing you can be sure of is that you will never buy a part
that is slower than its specification.
All parameters will be better than the spec, but not all by the same
percentage.
Let me therefore discourage you from your elaborate plans. There is no
simple answer.
Peter Alfke
==============================
Craig Conway wrote:
| Quote: | I'm trying to determine the delay curve of a particular path in a
Virtex2Pro -5 from min timing to max, including all points in
between.
Obviously I can get the two end points (min and max) from the timing
analyzer, but I assume that points between the two don't necessarily
fall on
a straight line. I considered also plotting the max timing of the
other
speed grades (-7 and -6), but I don't know what their relationship to
each
other is, so I wouldn't know exactly where to plot them relative to
the -5
max endpoint.
If anyone knows where performance graphs might exist in the Xilinx
documenation, or what the relationship of speed grades to each other
is, I'd
be most appreciative of a response.
Thanks! |
|
|
| Back to top |
|
|
Craig Conway
Guest
|
| Posted:
Wed Dec 15, 2004 7:05 pm Post subject:
Re: Xilinx speed grading |
|
|
Peter,
Thanks for responding. I understand pretty well the reasons behind speed
binning and how artificial the boundaries are; however, there must be some
overall criteria Xilinx uses to determine where to set those boundaries.
When they bin their parts, they must be measuring several parameters and
deciding that the aggregation of those measurements must be in a certain
range to qualify as a -6. How does Xilinx decide what that range is?
Craig
"Peter" <peter@xilinx.com> wrote in message
news:1103072858.873114.286400@f14g2000cwb.googlegroups.com...
| Quote: | Craig, remember that "speed grades" are an artificial way of
segregating devices that are naturally made with a continuum of
performance parameters. To accomodate the unavoidable manufacturing
spread, IC manufacturers sort the devices into bins, so that they can
guarantee performance, but also sell the devices that came out slow or
"not so fast".
In a perfect world, all parameters would scale perfectly, i.e. a device
marked slow would have all its delays longer by the same factor, as
compared to the devices labeled fast.
The world is not perfect.
The only thing you can be sure of is that you will never buy a part
that is slower than its specification.
All parameters will be better than the spec, but not all by the same
percentage.
Let me therefore discourage you from your elaborate plans. There is no
simple answer.
Peter Alfke
==============================
Craig Conway wrote:
I'm trying to determine the delay curve of a particular path in a
Virtex2Pro -5 from min timing to max, including all points in
between.
Obviously I can get the two end points (min and max) from the timing
analyzer, but I assume that points between the two don't necessarily
fall on
a straight line. I considered also plotting the max timing of the
other
speed grades (-7 and -6), but I don't know what their relationship to
each
other is, so I wouldn't know exactly where to plot them relative to
the -5
max endpoint.
If anyone knows where performance graphs might exist in the Xilinx
documenation, or what the relationship of speed grades to each other
is, I'd
be most appreciative of a response.
Thanks!
|
|
|
| Back to top |
|
|
Austin Lesea
Guest
|
| Posted:
Wed Dec 15, 2004 9:02 pm Post subject:
Re: Xilinx speed grading |
|
|
Craig,
Before we fabricate the device (ie after we tape out) we examine the
spice model corners, and decide what range of speed we can expect. We
then decide to bin based on a yield goal into each speed bin.
Once we have the parts, we fine tune the process with our fab partners
to get what we designed to (after all, if the models don't match, how in
the hell can we know if it will work?). Then, by construction, we have
the yield (or better) to the bins we desired.
Every technology node is different (process changes with each generation).
So, take Peter's advice,
Austin
Craig Conway wrote:
| Quote: | Peter,
Thanks for responding. I understand pretty well the reasons behind speed
binning and how artificial the boundaries are; however, there must be some
overall criteria Xilinx uses to determine where to set those boundaries.
When they bin their parts, they must be measuring several parameters and
deciding that the aggregation of those measurements must be in a certain
range to qualify as a -6. How does Xilinx decide what that range is?
Craig
"Peter" <peter@xilinx.com> wrote in message
news:1103072858.873114.286400@f14g2000cwb.googlegroups.com...
Craig, remember that "speed grades" are an artificial way of
segregating devices that are naturally made with a continuum of
performance parameters. To accomodate the unavoidable manufacturing
spread, IC manufacturers sort the devices into bins, so that they can
guarantee performance, but also sell the devices that came out slow or
"not so fast".
In a perfect world, all parameters would scale perfectly, i.e. a device
marked slow would have all its delays longer by the same factor, as
compared to the devices labeled fast.
The world is not perfect.
The only thing you can be sure of is that you will never buy a part
that is slower than its specification.
All parameters will be better than the spec, but not all by the same
percentage.
Let me therefore discourage you from your elaborate plans. There is no
simple answer.
Peter Alfke
==============================
Craig Conway wrote:
I'm trying to determine the delay curve of a particular path in a
Virtex2Pro -5 from min timing to max, including all points in
between.
Obviously I can get the two end points (min and max) from the timing
analyzer, but I assume that points between the two don't necessarily
fall on
a straight line. I considered also plotting the max timing of the
other
speed grades (-7 and -6), but I don't know what their relationship to
each
other is, so I wouldn't know exactly where to plot them relative to
the -5
max endpoint.
If anyone knows where performance graphs might exist in the Xilinx
documenation, or what the relationship of speed grades to each other
is, I'd
be most appreciative of a response.
Thanks!
|
|
|
| Back to top |
|
|
Jules P
Guest
|
| Posted:
Wed Dec 15, 2004 10:07 pm Post subject:
Re: Xilinx speed grading |
|
|
Austin,
just a quick question. Do many devices fail to meet your parametric
specification, i.e. have performance that does not satisfy the lowest
speed grade?
Thanks,
On Wed, 15 Dec 2004 08:02:39 -0800, Austin Lesea <austin@xilinx.com>
wrote:
| Quote: | Craig,
Before we fabricate the device (ie after we tape out) we examine the
spice model corners, and decide what range of speed we can expect. We
then decide to bin based on a yield goal into each speed bin.
Once we have the parts, we fine tune the process with our fab partners
to get what we designed to (after all, if the models don't match, how in
the hell can we know if it will work?). Then, by construction, we have
the yield (or better) to the bins we desired.
Every technology node is different (process changes with each generation).
So, take Peter's advice,
Austin
Craig Conway wrote:
Peter,
Thanks for responding. I understand pretty well the reasons behind speed
binning and how artificial the boundaries are; however, there must be some
overall criteria Xilinx uses to determine where to set those boundaries.
When they bin their parts, they must be measuring several parameters and
deciding that the aggregation of those measurements must be in a certain
range to qualify as a -6. How does Xilinx decide what that range is?
Craig
"Peter" <peter@xilinx.com> wrote in message
news:1103072858.873114.286400@f14g2000cwb.googlegroups.com...
Craig, remember that "speed grades" are an artificial way of
segregating devices that are naturally made with a continuum of
performance parameters. To accomodate the unavoidable manufacturing
spread, IC manufacturers sort the devices into bins, so that they can
guarantee performance, but also sell the devices that came out slow or
"not so fast".
In a perfect world, all parameters would scale perfectly, i.e. a device
marked slow would have all its delays longer by the same factor, as
compared to the devices labeled fast.
The world is not perfect.
The only thing you can be sure of is that you will never buy a part
that is slower than its specification.
All parameters will be better than the spec, but not all by the same
percentage.
Let me therefore discourage you from your elaborate plans. There is no
simple answer.
Peter Alfke
==============================
Craig Conway wrote:
I'm trying to determine the delay curve of a particular path in a
Virtex2Pro -5 from min timing to max, including all points in
between.
Obviously I can get the two end points (min and max) from the timing
analyzer, but I assume that points between the two don't necessarily
fall on
a straight line. I considered also plotting the max timing of the
other
speed grades (-7 and -6), but I don't know what their relationship to
each
other is, so I wouldn't know exactly where to plot them relative to
the -5
max endpoint.
If anyone knows where performance graphs might exist in the Xilinx
documenation, or what the relationship of speed grades to each other
is, I'd
be most appreciative of a response.
Thanks!
|
|
|
| Back to top |
|
|
B. Joshua Rosen
Guest
|
| Posted:
Wed Dec 15, 2004 11:17 pm Post subject:
Re: Xilinx speed grading |
|
|
On Wed, 15 Dec 2004 17:07:57 +0000, Jules P wrote:
| Quote: | Austin,
just a quick question. Do many devices fail to meet your parametric
specification, i.e. have performance that does not satisfy the lowest
speed grade?
Thanks,
On Wed, 15 Dec 2004 08:02:39 -0800, Austin Lesea <austin@xilinx.com
wrote:
Craig,
Before we fabricate the device (ie after we tape out) we examine the
spice model corners, and decide what range of speed we can expect. We
then decide to bin based on a yield goal into each speed bin.
Once we have the parts, we fine tune the process with our fab partners
to get what we designed to (after all, if the models don't match, how in
the hell can we know if it will work?). Then, by construction, we have
the yield (or better) to the bins we desired.
Every technology node is different (process changes with each generation).
So, take Peter's advice,
Austin
Craig Conway wrote:
Peter,
Thanks for responding. I understand pretty well the reasons behind speed
binning and how artificial the boundaries are; however, there must be some
overall criteria Xilinx uses to determine where to set those boundaries.
When they bin their parts, they must be measuring several parameters and
deciding that the aggregation of those measurements must be in a certain
range to qualify as a -6. How does Xilinx decide what that range is?
Craig
"Peter" <peter@xilinx.com> wrote in message
news:1103072858.873114.286400@f14g2000cwb.googlegroups.com...
Craig, remember that "speed grades" are an artificial way of
segregating devices that are naturally made with a continuum of
performance parameters. To accomodate the unavoidable manufacturing
spread, IC manufacturers sort the devices into bins, so that they can
guarantee performance, but also sell the devices that came out slow or
"not so fast".
In a perfect world, all parameters would scale perfectly, i.e. a device
marked slow would have all its delays longer by the same factor, as
compared to the devices labeled fast.
The world is not perfect.
The only thing you can be sure of is that you will never buy a part
that is slower than its specification.
All parameters will be better than the spec, but not all by the same
percentage.
Let me therefore discourage you from your elaborate plans. There is no
simple answer.
Peter Alfke
==============================
Craig Conway wrote:
I'm trying to determine the delay curve of a particular path in a
Virtex2Pro -5 from min timing to max, including all points in
between.
Obviously I can get the two end points (min and max) from the timing
analyzer, but I assume that points between the two don't necessarily
fall on
a straight line. I considered also plotting the max timing of the
other
speed grades (-7 and -6), but I don't know what their relationship to
each
other is, so I wouldn't know exactly where to plot them relative to
the -5
max endpoint.
If anyone knows where performance graphs might exist in the Xilinx
documenation, or what the relationship of speed grades to each other
is, I'd
be most appreciative of a response.
Thanks!
|
If they had a significant number of parts that failed to meet the lowest
speed grade but otherwise worked they would just introduce a lower speed
grade. In fact Xilinx offers parts that don't work completely. Some parts
have slight defects which effect only a subset of designs. You can give
Xilinx a bit file and a set of test patterns and they will test their
slightly defective parts to see if they will work for your application, if
they do they will sell them to you at a huge discount. It's the same
principle as hog butchers, they sell everything except the squeal. |
|
| Back to top |
|
|
Austin Lesea
Guest
|
| Posted:
Thu Dec 16, 2004 12:11 am Post subject:
Re: Xilinx speed grading |
|
|
"everything except the squeal"?
Now that is pretty graphic.
EasyPath(tm) is no different that selling an FPGA that has a laser fuse
blown to replace a defective column of logic.
Gee, I wonder who does that with every part they sell?
Get over it: a few bad memory bits (out of 20 million) is not a
"slightly defective" part -- it is >99.99985% perfect.
Austin |
|
| Back to top |
|
|
rickman
Guest
|
| Posted:
Thu Dec 16, 2004 1:40 am Post subject:
Re: Xilinx speed grading |
|
|
Austin Lesea wrote:
| Quote: |
"everything except the squeal"?
Now that is pretty graphic.
EasyPath(tm) is no different that selling an FPGA that has a laser fuse
blown to replace a defective column of logic.
Gee, I wonder who does that with every part they sell?
Get over it: a few bad memory bits (out of 20 million) is not a
"slightly defective" part -- it is >99.99985% perfect.
|
Isn't being 99.99985% perfect like being 0.00015% pregnant? ;)
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX |
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| Back to top |
|
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Peter
Guest
|
| Posted:
Thu Dec 16, 2004 2:55 am Post subject:
Re: Xilinx speed grading |
|
|
ASICs would be very happy if they could promise 99.99985% testability
....
Peter Alfke |
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| Back to top |
|
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Austin Lesea
Guest
|
| Posted:
Thu Dec 16, 2004 3:31 am Post subject:
Re: Xilinx speed grading |
|
|
Rick,
The simple answer? No, it is not.
One bad bit doth not a bad chip make.
If it did, the entire RAM business would be out of business.
All RAM (and EPROM) use redundant rows or columns, and redundant repair
(or self repair) structures.
Music CD's run with error correction correcting errors all the time
(there is practically no interval where there is a single packet with 0
errors).
Cell phones work with forward error correction, and they too run in the
errored region all the time.
Austin
rickman wrote:
| Quote: | Austin Lesea wrote:
"everything except the squeal"?
Now that is pretty graphic.
EasyPath(tm) is no different that selling an FPGA that has a laser fuse
blown to replace a defective column of logic.
Gee, I wonder who does that with every part they sell?
Get over it: a few bad memory bits (out of 20 million) is not a
"slightly defective" part -- it is >99.99985% perfect.
Isn't being 99.99985% perfect like being 0.00015% pregnant? ;)
|
|
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| Back to top |
|
|
Symon
Guest
|
| Posted:
Thu Dec 16, 2004 2:51 pm Post subject:
Re: Xilinx speed grading |
|
|
Hi Austin,
It would seem to me that the laser fuse method is a much better idea than
EasyPath(tm). As you say in another post, we live in an errored world! With
the laser fuse, yield is higher, price is lower. With EasyPath(tm), you
scrabble around in the defect bin to find dodgy parts which fit the user's
design. The design then must remain unchanged, because a recompile might hit
a bad bit in your installed base. Maybe you should rename it
DifficultPath(tm)? Or am I missing something? No worse than an ASIC, I
guess.
Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:cpq28u$9kt2@cliff.xsj.xilinx.com...
| Quote: | EasyPath(tm) is no different that selling an FPGA that has a laser fuse
blown to replace a defective column of logic.
Gee, I wonder who does that with every part they sell? |
|
|
| Back to top |
|
|
B. Joshua Rosen
Guest
|
| Posted:
Thu Dec 16, 2004 7:29 pm Post subject:
Re: Xilinx speed grading |
|
|
On Wed, 15 Dec 2004 11:11:26 -0800, Austin Lesea wrote:
| Quote: | "everything except the squeal"?
The expression "everything except the squeal" comes from Upton Sinclair's |
book The Jungle about the Chicago Stockyards. The Jungle caused Congress
to pass the 1906 Clean Food and Drug act that created the FDA.
| Quote: |
Now that is pretty graphic.
EasyPath(tm) is no different that selling an FPGA that has a laser fuse
blown to replace a defective column of logic.
Gee, I wonder who does that with every part they sell?
Get over it: a few bad memory bits (out of 20 million) is not a
"slightly defective" part -- it is >99.99985% perfect.
Austin
|
I didn't say there was anything wrong with EasyPath it's a good idea. I
was just making the point that no chip company is going to throw out a
part if there is a way to sell it. EasyPath allow you to sell parts that
work with specific bit streams but not with every bit stream. The customer
benefits by getting a much lower price at the cost of giving up the
flexibility of being able to drop in a different bit stream. The OP was
asking about parts that are slower than the slowest speed grade, I was
saying if there were any significant number of parts that were failing
to meet the lowest speed grade you would simply add a lower grade. It
would be bad business to do anything else. The farmstand on my corner does
the same thing. At the end of August they sell cases of Tomatoe seconds
for $6 a case. The tomatoes are fine for sauces, but they are ugly enough
that you don't want to put them in a salad. I buy a case of EasyPath
tomatoes every year and use them to make a years supply of spaghetti sauce. |
|
| Back to top |
|
|
Austin Lesea
Guest
|
| Posted:
Thu Dec 16, 2004 8:45 pm Post subject:
Re: Xilinx speed grading |
|
|
B,
Your analogies are so much fun!
Sounds like we are in "violent agreement."
Austin
B. Joshua Rosen wrote:
| Quote: | On Wed, 15 Dec 2004 11:11:26 -0800, Austin Lesea wrote:
"everything except the squeal"?
The expression "everything except the squeal" comes from Upton Sinclair's
book The Jungle about the Chicago Stockyards. The Jungle caused Congress
to pass the 1906 Clean Food and Drug act that created the FDA.
Now that is pretty graphic.
EasyPath(tm) is no different that selling an FPGA that has a laser fuse
blown to replace a defective column of logic.
Gee, I wonder who does that with every part they sell?
Get over it: a few bad memory bits (out of 20 million) is not a
"slightly defective" part -- it is >99.99985% perfect.
Austin
I didn't say there was anything wrong with EasyPath it's a good idea. I
was just making the point that no chip company is going to throw out a
part if there is a way to sell it. EasyPath allow you to sell parts that
work with specific bit streams but not with every bit stream. The customer
benefits by getting a much lower price at the cost of giving up the
flexibility of being able to drop in a different bit stream. The OP was
asking about parts that are slower than the slowest speed grade, I was
saying if there were any significant number of parts that were failing
to meet the lowest speed grade you would simply add a lower grade. It
would be bad business to do anything else. The farmstand on my corner does
the same thing. At the end of August they sell cases of Tomatoe seconds
for $6 a case. The tomatoes are fine for sauces, but they are ugly enough
that you don't want to put them in a salad. I buy a case of EasyPath
tomatoes every year and use them to make a years supply of spaghetti sauce. |
|
|
| Back to top |
|
|
Austin Lesea
Guest
|
| Posted:
Thu Dec 16, 2004 9:04 pm Post subject:
Re: Xilinx speed grading |
|
|
Symon,
Why are fuses so much better? They cost in area (redundant circuits
which drive down yield), and they cost in test (have to blow them).
So the customer pays twice on every part for perfection more than they
would for a non-redundant part, and certainly they pay more for an
EasyPath(tm) part.
The fact that EasyPath parts pass a full qualification program proves
their reliability, so that is not an issue either.
We do test 100% of the LUTs, IOs, clock resources, and some other
features on every EasyPath part. That is how we just introduced the
'ECO feature'. If you need to change IO strength (very common), or
change the logic in a LUT (that darned inversion you forgot), you can do
so without any changes or worries to the test program.
If worst comes to worst, and you need to change something not tested, it
turns out the probabilities that the new pattern will work are amazingly
high. We will work with you to make the change, and tell you what your
exposure is for parts already shipped (to operate with the new pattern).
Can't do that with an ASIC -- they are all garbage immediately for the
smallest error!
That is why 'HardtoCopy' is what we abandoned ('Hardwire') years ago:
no profit, no margins, sucks engineering resources dry, immense costs,
tremendous headaches, unhappy customers -- hey that sounds just like the
ASIC business!
The structured ASIC business has turned out to be a big yawn - so small
$ and units that it is hard to see it on any charts. Who cares?
Non-story. The finance folks have already written it off, and moved on
to the next shell and pea game.
Getting back to EP, it turns out that most failing parts (restricted
info for exact number) are bad because of one or two config bits. Also,
if the volume is high enough for the EasyPath customer, we start wafers
for just that customer, and test to their pattern. We would never know
if these are perfect parts, or not, and we wouldn't care either (as we
saved the requisite amount of money to offer the parts at the price we
do). Just like an ASIC, except it has a higher test coverage, and lower
PPM failure number!
"Dodgy" makes it sound like we are dumpster diving.
In reality, it is a very clever, very efficient, very useful, very cost
effective product flow.
I think that certain frustrated competitors have promoted the 'EasyPath
= Flawed Goods' FUD story out of desparation.
When one can introduce a whole new and useful product (profitable, too)
line with $0 of IC design engineering (no tapeouts, no design), that has
got to hurt!
Austin
Symon wrote:
| Quote: | Hi Austin,
It would seem to me that the laser fuse method is a much better idea than
EasyPath(tm). As you say in another post, we live in an errored world! With
the laser fuse, yield is higher, price is lower. With EasyPath(tm), you
scrabble around in the defect bin to find dodgy parts which fit the user's
design. The design then must remain unchanged, because a recompile might hit
a bad bit in your installed base. Maybe you should rename it
DifficultPath(tm)? Or am I missing something? No worse than an ASIC, I
guess.
Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:cpq28u$9kt2@cliff.xsj.xilinx.com...
EasyPath(tm) is no different that selling an FPGA that has a laser fuse
blown to replace a defective column of logic.
Gee, I wonder who does that with every part they sell?
|
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