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Fred Bartoli · Guest

Hello,

I have the following code :

width = 128

architecture bhv of yy is
function Stop_Sense ( IsSigCell, StopNextCells : std_ulogic_vector(Width-1
downto 0);
CurrentCell : natural range 0 to Width-1;
LookAheadDepth : natural range 1 to 16
) return std_ulogic is
begin
L1:for i in 1 to LookAheadDepth - 1 loop
if (CurrentCell - i) >= 0 then
if StopNextCells(CurrentCell - i) = '1' then
return '1';
else
if IsSigCell(CurrentCell - i) = '1' then
exit;
end if;
end if;
end if;
end loop;
return '0';
end;

signal StopNextCells : std_ulogic_vector (Width-1 downto 0);
signal StopCell : std_ulogic_vector (Width-1 downto 0);
signal IsBoundaryCell : std_ulogic_vector (Width-1 downto 0);

begin
..
..

StopCells: for i in 0 to Width-1 generate
StopCell(i) <= Stop_Sense(IsBoundaryCell, StopNextCells, i, N1_max);
end generate;

..
..
end bhv;

The function returns '1' when the StopNextCells vector contains at least a
'1' after the CurrentCell position and before the CurrentCell+LookAheadDepth
position and the first '1' in the IsSigCell vector.

Works OK in simulation, but quartus synthesize this as a simple OR on the
next N1_max StopNextCells positions which is not the intended behaviour.

What am I doing wrong in the code ?

BTW, I have 2 of these entities, plus as much of 2 other kinds of this, so I
have the equivalent of 1024 of these functions. Is there a more efficient
way to pack the logic ?

--
Thanks,
Fred.

Subroto Datta · Guest

Hi Fred,

Thank you for providing the code. The results in Quartus II 4.1, 4.2,
are incorrect. If you the "exit" statement in Stop_Sense with a
return '0', this will synthesize correctly in 4.1 and 4.2. This
problem will be fixed in Quartus II 5.0.The modified VHDL is shown
below:
library ieee;
use ieee.std_logic_1164.all;

entity yy is

generic (
width : natural := 4);

port (
stopcell : out std_ulogic_vector(width - 1
downto 0);
isboundarycell, stopnextcells : in std_ulogic_vector(width -1
downto 0));

end yy;

architecture bhv of yy is
function Stop_Sense ( IsSigCell, StopNextCells :
std_ulogic_vector(Width-1
downto 0);
CurrentCell : natural range 0 to Width-1;
LookAheadDepth : natural range 1 to 16
) return std_ulogic is
begin
L1:for i in 1 to LookAheadDepth - 1 loop
if (CurrentCell - i) >= 0 then
if StopNextCells(CurrentCell - i) = '1' then
return '1';
elsif IsSigCell(CurrentCell - i) = '1' then
return '0'; -- replaced exit statement !!!!
end if;
end if;
end loop;
return '0';
end;

--signal StopNextCells : std_ulogic_vector (Width-1 downto 0);
--signal StopCell : std_ulogic_vector (Width-1 downto 0);
--signal IsBoundaryCell : std_ulogic_vector (Width-1 downto 0);

begin

StopCells: for i in 0 to Width-1 generate

StopCell(i) <= Stop_Sense(IsBoundaryCell, StopNextCells, i, 2);
end generate;

end bhv;

Hope this helps,
- Subroto Datta
Altera Corp.

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